AV-51002
2017.02.10
1-85
Minimum Configuration Time Estimation
Active Serial(108)
Fast Passive Parallel(109)
Variant
Member Code
Width
DCLK (MHz) Minimum Configura‐
tion Time (ms)
Width
DCLK (MHz)
Minimum Configuration Time
(ms)
A1
A3
A5
A7
B1
B3
B5
B7
C3
C7
D3
D7
B3
B5
D3
D5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
178
178
255
255
344
344
465
465
178
255
344
465
465
465
465
465
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
36
36
51
51
69
69
93
93
36
51
69
93
93
93
93
93
Arria V GX
Arria V GT
Arria V SX
Arria V ST
Related Information
Configuration Files on page 1-83
(108)
DCLKfrequency of 100 MHz using external CLKUSR.
Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
(109)
Arria V GX, GT, SX, and ST Device Datasheet
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