AV-51002
2017.02.10
2-49
DPA Mode High-Speed I/O Specifications
DPA Mode High-Speed I/O Specifications
Table 2-42: High-Speed I/O Specifications for Arria V GZ Devices
When J = 3 to 10, use the serializer/deserializer (SERDES) block.
When J = 1 or 2, bypass the SERDES block.
C3, I3L
Typ
C4, I4
Symbol
Conditions
Unit
Min
Max
Min
Typ
Max
DPA run length
—
—
—
10000
—
—
10000
UI
Figure 2-3: DPA Lock Time Specification with DPA PLL Calibration Enabled
rx_reset
DPA Lock Time
256 data
rx_dpa_locked
256 data
transitions
96 slow
96 slow
256 data
clock cycles transitions
clock cycles transitions
Table 2-43: DPA Lock Time Specifications for Arria V GZ Devices
e DPA lock time is for one channel.
One data transition is defined as a 0-to-1 or 1-to-0 transition.
e DPA lock time stated in this table applies to both commercial and industrial grade.
Standard
Training Pattern
Number of Data Transitions Number of Repetitions per
in One Repetition of the
Training Pattern
Maximum
256 Data Transitions (201)
SPI-4
00000000001111111111
2
128
640 data transitions
(201)
is is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
Arria V GZ Device Datasheet
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