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5ASXMB3E4F31I3N 参数 Datasheet PDF下载

5ASXMB3E4F31I3N图片预览
型号: 5ASXMB3E4F31I3N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 670MHz, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 时钟LTE可编程逻辑
文件页数/大小: 184 页 / 1809 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51002  
2017.02.10  
2-48  
Receiver High-Speed I/O Specifications  
C3, I3L  
Typ  
C4, I4  
Typ  
Symbol  
Conditions  
Unit  
Min  
Max  
Min  
Max  
SERDES factor J = 3 to 10  
150  
1250  
150  
1050  
Mbps  
(192) (193) (194) (195) (196) (197)  
,
,
,
,
,
SERDES factor J ≥ 4  
150  
1600  
150  
1250  
Mbps  
LVDS RX with DPA  
True Differential I/O  
Standards - fHSDRDPA  
(data rate)  
(193) (195) (196) (197)  
,
,
,
(198)  
(198)  
(199)  
(199)  
(198)  
(198)  
(199)  
(199)  
SERDES factor J = 2,  
uses DDR Registers  
Mbps  
Mbps  
SERDES factor J = 1,  
uses SDR Register  
(198)  
(198)  
(200)  
(199)  
(198)  
(198)  
(200)  
(199)  
SERDES factor J = 3 to 10  
Mbps  
Mbps  
SERDES factor J = 2,  
uses DDR Registers  
fHSDR (data rate)  
(198)  
(199)  
(198)  
(199)  
SERDES factor J = 1,  
uses SDR Register  
Mbps  
(192)  
e FMAX specification is based on the fast clock used for serial data. e interface FMAX is also dependent on the parallel clock domain which is  
design dependent and requires timing analysis.  
(193)  
(194)  
(195)  
(196)  
(197)  
(198)  
Arria V GZ RX LVDS will need DPA. For Arria V GZ TX LVDS, the receiver side component must have DPA.  
Arria V GZ LVDS serialization and de-serialization factor needs to be x4 and above.  
Requires package skew compensation with PCB trace length.  
Do not mix single-ended I/O buffer within LVDS I/O bank.  
Chip-to-chip communication only with a maximum load of 5 pF.  
e minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or  
local) that you use. e I/O differential buffer and input register do not have a minimum toggle rate.  
e maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and  
the signal integrity simulation is clean.  
(199)  
(200)  
You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board  
skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.  
Arria V GZ Device Datasheet  
Send Feedback  
Altera Corporation  
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