AV-51002
2017.02.10
2-46
Transmitter High-Speed I/O Specifications
C3, I3L
Typ
C4, I4
Typ
Symbol
Conditions
Unit
Min
Max
Min
Max
(184)
(184)
SERDES factor J = 3 to 10
—
1250
—
1050
Mbps
(182) (183)
,
(184)
(184)
SERDES factor J ≥ 4
—
1600
—
1250
Mbps
LVDS TX with DPA
True Differential I/O
Standards - fHSDR (data rate)
(185) (186) (187) (188)
,
,
,
(184)
(184)
(184)
(189)
(189)
(184)
(184)
(184)
(189)
(189)
SERDES factor J = 2,
uses DDR Registers
—
—
—
—
—
—
Mbps
Mbps
Mbps
SERDES factor J = 1,
uses SDR Register
SERDES factor J = 4 to 10 (191)
Emulated Differential I/O
Standards with ree
840
840
External Output Resistor
Networks - fHSDR (data rate)
(190)
(182)
If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
(183)
e FMAX specification is based on the fast clock used for serial data. e interface FMAX is also dependent on the parallel clock domain which is
design dependent and requires timing analysis.
(184)
e minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or
local) that you use. e I/O differential buffer and input register do not have a minimum toggle rate.
Arria V GZ RX LVDS will need DPA. For Arria V GZ TX LVDS, the receiver side component must have DPA.
Requires package skew compensation with PCB trace length.
Do not mix single-ended I/O buffer within LVDS I/O bank.
Chip-to-chip communication only with a maximum load of 5 pF.
e maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and
the signal integrity simulation is clean.
(185)
(186)
(187)
(188)
(189)
(190)
(191)
You must calculate the lefover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin,
transmitter channel-to-channel skew, and receiver sampling margin to determine lefover timing margin.
When using True LVDS RX channels for emulated LVDS TX channel, only serialization factors 1 and 2 are supported.
Arria V GZ Device Datasheet
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