AV-51002
2017.02.10
2-53
DLL Range Specifications
DLL Range Specifications
Table 2-47: DLL Range Specifications for Arria V GZ Devices
Arria V GZ devices support memory interface frequencies lower than 300 MHz, although the reference clock that feeds the DLL must be at least
300 MHz. To support interfaces below 300 MHz, multiply the reference clock feeding the DLL to ensure the frequency is within the supported
range of the DLL.
Parameter
C3, I3L
C4, I4
Unit
DLL operating frequency range
300 – 890
300 – 890
MHz
DQS Logic Block Specifications
Table 2-48: DQS Phase Offset Delay Per Setting for Arria V GZ Devices
e typical value equals the average of the minimum and maximum values.
e delay settings are linear with a cumulative delay variation of 40 ps for all speed grades. For example, when using a –3 speed grade and applying
a 10-phase offset setting to a 90° phase shif at 400 MHz, the expected average cumulative delay is [625 ps + (10 × 11 ps) 20 ps] = 735 ps 20 ps.
Speed Grade
Min
8
Max
15
Unit
ps
C3, I3L
C4, I4
8
16
ps
Table 2-49: DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Arria V GZ Devices
is error specification is the absolute maximum and minimum error. For example, skew on three DQS delay buffers in a –3 speed grade is 84 ps
or 42 ps.
Number of DQS Delay Buffers
C3, I3L
30
C4, I4
32
Unit
ps
1
2
3
60
64
ps
90
96
ps
Arria V GZ Device Datasheet
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