AV-51002
2017.02.10
2-45
Transmitter High-Speed I/O Specifications
C3, I3L
Typ
C4, I4
Symbol
Conditions
Unit
Min
Max
Min
Typ
Max
fHSCLK_in (input clock
frequency) True Differential
I/O Standards (179)
Clock boost factor
W = 1 to 40 (180)
5
—
625
5
—
525
MHz
fHSCLK_in (input clock
frequency) Single Ended I/O
Standards
Clock boost factor
W = 1 to 40 (180)
5
5
5
—
—
—
625
420
5
5
5
—
—
—
525
420
MHz
MHz
MHz
fHSCLK_in (input clock
frequency) Single Ended I/O
Standards
Clock boost factor
W = 1 to 40 (180)
fHSCLK_OUT (output clock
frequency)
—
625 (181)
525 (181)
Transmitter High-Speed I/O Specifications
Table 2-40: Transmitter High-Speed I/O Specifications for Arria V GZ Devices
When J = 3 to 10, use the serializer/deserializer (SERDES) block.
When J = 1 or 2, bypass the SERDES block.
(179)
is only applies to DPA and sof-CDR modes.
(180)
Clock Boost Factor (W) is the ratio between the input data rate to the input clock rate.
(181)
is is achieved by using the LVDS clock network.
Arria V GZ Device Datasheet
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