Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Term
Definition
VIH(AC)
VIH(DC)
VIL
High-level AC input voltage.
High-level DC input voltage.
Voltage input low: The maximum positive voltage applied to the input which is accepted by the device as a logic low.
VIL (AC)
VIL (DC)
VIN
Low-level AC input voltage.
Low-level DC input voltage.
DC input voltage.
VOCM
VOD
Output common mode voltage: The common mode of the differential signal at the transmitter.
Output differential voltage swing: The difference in voltage between the positive and complementary conductors of a differential
transmission line at the transmitter. VOD = VOH – VOL
.
VOH
Voltage output high: The maximum positive voltage from an output which the device considers is accepted as the minimum positive
high level.
VOL
Voltage output low: The maximum positive voltage from an output which the device considers is accepted as the maximum positive
low level.
VOS
Output offset voltage: VOS = (VOH + VOL) / 2.
VOX (AC)
VREF
AC differential Output cross point voltage: The voltage at which the differential output signals must cross.
Reference voltage for SSTL, HSTL, and HSUL I/O Standards.
VREF(AC)
AC input reference voltage for SSTL, HSTL, and HSUL I/O Standards. VREF(AC) = VREF(DC) + noise. The peak-to-peak AC noise on
VREF should not exceed 2% of VREF(DC)
.
VREF(DC)
VSWING (AC)
VSWING (DC)
VTT
DC input reference voltage for SSTL, HSTL, and HSUL I/O Standards.
AC differential input voltage: AC Input differential voltage required for switching.
DC differential input voltage: DC Input differential voltage required for switching.
Termination voltage for SSTL, HSTL, and HSUL I/O Standards.
VX (AC)
AC differential Input cross point voltage: The voltage at which the differential input signals must cross.
Intel® MAX® 10 FPGA Device Datasheet
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