Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Date
Version
Changes
November 2015
2015.11.02
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Added description to Maximum Allowed Overshoot During Transitions over a 11.4-Year Time Frame topic.
Added ADC_VREF Pin Leakage Current for Intel MAX 10 Devices table.
Updated the condition for "Bus-hold high, sustaining current" parameter from "VIN < VIL (minimum)" to "VIN < VIH
(minimum)" in Bus Hold Parameters table.
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Added –A6 speed grade in the following tables:
— Intel MAX 10 Device Grades and Speed Grades Supported
— Series OCT without Calibration Specifications for Intel MAX 10 Devices
— Clock Tree Specifications for Intel MAX 10 Devices
— Embedded Multiplier Specifications for Intel MAX 10 Devices
— Memory Block Performance Specifications for Intel MAX 10 Devices
— True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— Emulated RSDS_E_1R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for Intel MAX 10 Dual Supply Devices
— IOE Programmable Delay on Row Pins for Intel MAX 10 Devices
— IOE Programmable Delay on Column Pins for Intel MAX 10 Devices
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Updated the maximum value for input clock cycle-to-cycle jitter (tINJITTER_CCJ) with FINPFD < 100 MHz condition from 750 ps
to ±750 ps in PLL Specifications for Intel MAX 10 Devices table.
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Updated the dual supply mode performance in Embedded Multiplier Specifications for Intel MAX 10 Devices table.
Updated the dual supply mode performance in Memory Block Performance Specifications for Intel MAX 10 Devices table.
Added typical specifications in Internal Oscillator Frequencies for Intel MAX 10 Devices table.
Updated specifications in UFM Performance Specifications for Intel MAX 10 Devices table.
Updated sampling window specifications in LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for
Intel MAX 10 Dual Supply Devices table.
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Updated IOE programmable delay for row and column pins.
Changed instances of Quartus II to Quartus Prime.
June 2015
2015.06.12
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Updated the maximum values in Internal Weak Pull-Up Resistor for Intel MAX 10 Devices table.
Removed Internal Weak Pull-Up Resistor equation.
Updated the note for input resistance and input capacitance parameters in the ADC Performance Specifications table for
both single supply and dual supply devices. Note: Download the SPICE models for simulation.
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Added a note to AC Accuracy - THD, SNR, and SINAD parameters in the ADC Performance Specifications for Intel MAX 10
Dual Supply Devices table. Note: When using internal VREF, THD = 66 dB, SNR = 58 dB and SINAD = 57.5 dB for
dedicated ADC input channels.
Updated clock period jitter and cycle-to-cycle period jitter parameters in the Memory Output Clock Jitter Specifications for
Intel MAX 10 Devices table.
continued...
Intel® MAX® 10 FPGA Device Datasheet
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