Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
The Intel Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specific device
and design after you complete place-and-route.
Table 56.
I/O Timing for Intel MAX 10 Devices
These I/O timing parameters are for the 3.3-V LVTTL I/O standard with the maximum drive strength and fast slew rate for 10M08DAF484 device.
Symbol
Parameter
–C7, –I7
–0.750
1.180
–C8
Unit
ns
Tsu
Th
Global clock setup time
Global clock hold time
–0.808
1.215
5.575
5.467
ns
Tco
Tpd
Global clock to output delay
5.131
ns
Best case pin-to-pin propagation delay through one LUT
4.907
ns
Programmable IOE Delay
Programmable IOE Delay On Row Pins
Table 57.
IOE Programmable Delay on Row Pins for Intel MAX 10 Devices
The incremental values for the settings are generally linear. For exact values of each setting, refer to the Assignment Name column in the latest version of the
Intel Quartus Prime software.
The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Intel Quartus Prime software.
Parameter
Paths Affected
Number of Minimum
Maximum Offset
Slow Corner
Unit
Settings
Offset
Fast Corner
–I7
–C8
–A6
–C7
–C8
–I7
–A7
Input delay from
pin to internal
cells
Pad to I/O
dataout to core
7
8
2
0
0
0
0.815
0.924
0.479
0.873
1.831
1.811
1.874
1.871
1.922
ns
ns
ns
Input delay from
pin to input
register
Pad to I/O input
register
0.992
0.514
2.081
1.069
2.055
1.070
2.125
1.117
2.127
1.105
2.185
1.134
Delay from
I/O output
output register to register to pad
output pin
Intel® MAX® 10 FPGA Device Datasheet
62
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