Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Programmable IOE Delay for Column Pins
Table 58.
IOE Programmable Delay on Column Pins for Intel MAX 10 Devices
The incremental values for the settings are generally linear. For exact values of each setting, refer to the Assignment Name column in the latest version of the
Intel Quartus Prime software.
The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Intel Quartus Prime software.
Parameter
Paths Affected
Number of Minimum
Maximum Offset
Slow Corner
Unit
Settings
Offset
Fast Corner
–I7
–C8
–A6
–C7
–C8
–I7
–A7
Input delay from
pin to internal
cells
Pad to I/O
dataout to core
7
8
2
0
0
0
0.81
0.914
0.435
0.868
1.823
1.802
1.864
1.862
1.912
ns
ns
ns
Input delay from
pin to input
register
Pad to I/O input
register
0.981
0.466
2.06
2.032
0.97
2.101
1.013
2.102
1.001
2.161
1.028
Delay from
I/O output
0.971
output register to register to pad
output pin
Glossary
Table 59.
Glossary
Term
Definition
Receiver differential input discrete resistor (external to Intel MAX 10 devices).
RL
RSKM (Receiver input skew margin)
Sampling window (SW)
HIGH-SPEED I/O block: The total margin left after accounting for the sampling window and TCCS. RSKM = (TUI – SW – TCCS) / 2.
HIGH-SPEED I/O Block: The period of time during which the data must be valid to capture it correctly. The setup and hold times
determine the ideal strobe position in the sampling window.
Single-ended voltage referenced I/O
standard
The AC input signal values indicate the voltage levels at which the receiver must meet its timing specifications. The DC input signal
values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input
crosses the AC value, the receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide
predictable receiver timing in the presence of input waveform ringing.
continued...
Intel® MAX® 10 FPGA Device Datasheet
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