Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Term
Definition
High-speed receiver/transmitter input and output clock period.
tC
TCCS (Channelto- channel-skew)
HIGH-SPEED I/O block: The timing difference between the fastest and slowest output edges, including tCO variation and clock skew.
The clock is included in the TCCS measurement.
tcin
Delay from clock pad to I/O input register.
Delay from clock pad to I/O output.
tCO
tcout
Delay from clock pad to I/O output register.
HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.
Signal high-to-low transition time (80–20%).
Input register hold time.
tDUTY
tFALL
tH
Timing Unit Interval (TUI)
HIGH-SPEED I/O block: The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver
Input Clock Frequency Multiplication Factor) = tC/w).
tINJITTER
tOUTJITTER_DEDCLK
tOUTJITTER_IO
tpllcin
Period jitter on PLL clock input.
Period jitter on dedicated clock output driven by a PLL.
Period jitter on general purpose I/O driven by a PLL.
Delay from PLL inclk pad to I/O input register.
tpllcout
Delay from PLL inclk pad to I/O output register.
tRISE
Signal low-to-high transition time (20–80%).
tSU
Input register setup time.
VCM(DC)
VDIF(AC)
VDIF(DC)
VHYS
DC common mode input voltage.
AC differential input voltage: The minimum AC input differential voltage required for switching.
DC differential input voltage: The minimum DC input differential voltage required for switching.
Hysteresis for Schmitt trigger input.
VICM
Input common mode voltage: The common mode of the differential signal at the receiver.
VID
Input differential Voltage Swing: The difference in voltage between the positive and complementary conductors of a differential
transmission at the receiver.
VIH
Voltage input high: The minimum positive voltage applied to the input which is accepted by the device as a logic high.
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Intel® MAX® 10 FPGA Device Datasheet
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