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10M02SCU169C8G 参数 Datasheet PDF下载

10M02SCU169C8G图片预览
型号: 10M02SCU169C8G
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, PBGA169, 11 X 11 MM, 0.80 MM PITCH, ROHS COMPLIANT, UBGA-169]
分类和应用: 时钟可编程逻辑
文件页数/大小: 71 页 / 822 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Intel® MAX® 10 FPGA Device Datasheet  
M10-DATASHEET | 2017.12.15  
Date  
January 2016  
Version  
2016.01.22  
Changes  
Added description about automotive temperature devices in the Programming/Erasure Specifications table.  
Changed the pin capacitance to maximum values.  
Updated maximum TCCS specifications from 410 ps to 300 ps in the following tables:  
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices  
True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices  
— Emulated RSDS_E_1R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices  
True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices  
True LVDS Transmitter Timing Specifications for Intel MAX 10 Single Supply Devices  
True LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices  
— Emulated LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Single Supply Devices  
— Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices  
Added new table: True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Single Supply  
Devices.  
Updated maximum fHSCLK and HSIODR specifications for –A6, –C7, and –I7 speed grades in True LVDS Transmitter Timing  
Specifications for Intel MAX 10 Dual Supply Devices table.  
Updated SW specifications in the following tables:  
— LVDS Receiver Timing Specifications for Intel MAX 10 Single Supply Devices  
— LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for Intel MAX 10 Dual Supply Devices  
Updated maximum fHSCLK and HSIODR (high-speed I/O performance pin) specifications for –I6, –A6, –C7, –I7 speed  
grades in LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for Intel MAX 10 Dual Supply Devices  
table.  
Removed Internal Configuration Time information in the Uncompressed .rbf Sizes for Intel MAX 10 Devices table.  
Added Internal Configuration Time tables for uncompressed .rbf files and compressed .rbf files.  
Removed Preliminary tags for all tables.  
continued...  
Intel® MAX® 10 FPGA Device Datasheet  
67  
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