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10M02SCU169C8G 参数 Datasheet PDF下载

10M02SCU169C8G图片预览
型号: 10M02SCU169C8G
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, PBGA169, 11 X 11 MM, 0.80 MM PITCH, ROHS COMPLIANT, UBGA-169]
分类和应用: 时钟可编程逻辑
文件页数/大小: 71 页 / 822 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Intel® MAX® 10 FPGA Device Datasheet  
M10-DATASHEET | 2017.12.15  
Table 54.  
Internal Configuration Time for Intel MAX 10 Devices (Compressed .rbf)  
Compression ratio depends on design complexity. The minimum value is based on the best case (25% of original .rbf sizes) and the maximum value is based on  
the typical case (70% of original .rbf sizes).  
Device  
Internal Configuration Time (ms)  
Unencrypted/Encrypted  
Without Memory Initialization  
Min Max  
With Memory Initialization  
Min  
Max  
10M02  
10M04  
10M08  
10M16  
10M25  
10M40  
10M50  
0.3  
0.6  
0.6  
1.1  
1.1  
2.6  
2.6  
5.2  
10.7  
10.7  
17.9  
26.9  
66.1  
66.1  
1.0  
1.0  
1.4  
1.4  
3.2  
3.2  
13.9  
13.9  
22.3  
32.2  
82.2  
82.2  
Related Links  
Instant-on, Intel MAX 10 FPGA Configuration User Guide  
Provides more information about instant-on feature.  
Internal Configuration Timing Parameter  
Table 55.  
Internal Configuration Timing Parameter for Intel MAX 10 Devices  
Symbol  
Parameter  
Device  
Minimum  
182.8  
Maximum  
385.5  
Unit  
μs  
tCD2UM  
10M02, 10M04, 10M08, 10M16, 10M25  
10M40, 10M50  
CONF_DONE high to  
user mode  
275.3  
605.7  
μs  
I/O Timing  
The data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the link timing  
analysis.  
Intel® MAX® 10 FPGA Device Datasheet  
61  
 
 
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