Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications
Table 40.
True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply
Devices
True mini-LVDS transmitter is only supported at the bottom I/O banks. Emulated mini-LVDS_E_3R transmitter is supported at the output pin of all I/O banks.
Symbol
Parameter
Mode
–I6, –A6, –C7, –I7
Min Max
–A7
Typ
—
–C8
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min
5
Max
155
155
155
155
155
310
310
310
310
310
310
310
150
150
150
150
150
300
300
300
Min
5
Max
155
155
155
155
155
310
310
310
310
310
310
310
150
150
150
150
150
300
300
300
fHSCLK
Input clock frequency
(high-speed I/O
performance pin)
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
×10
×8
5
5
155
155
155
155
155
310
310
310
310
310
310
310
150
150
150
150
150
300
300
300
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
5
—
5
5
5
—
5
5
5
—
5
5
5
—
5
5
5
—
5
HSIODR
Data rate (high-speed
I/O performance pin)
100
80
70
40
20
10
5
100
80
70
40
20
10
5
—
100
80
70
40
20
10
5
—
—
—
—
—
fHSCLK
Input clock frequency
(low-speed I/O
performance pin)
—
5
5
—
5
5
5
—
5
5
5
—
5
5
5
—
5
5
5
—
5
HSIODR
Data rate (low-speed
I/O performance pin)
100
80
100
80
—
100
80
—
Mbps
continued...
Intel® MAX® 10 FPGA Device Datasheet
44
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