[AK4679]
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) (Audio I/F)
A reference clock of PLL is selected among the input clocks to BICK pin. The required clock to the CODEC is generated
by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table 5).
BICK input should be synchronized to LRCK input. Sampling frequency can be selected by FS3-0 bits (Table 6).
CODEC
DSP
MCKI
32fs or 64fs
1fs
BCLKx
BICK
SYNCx
LRCK
SDINx
SDTO
SDTI
SDOUTx
Figure 40. PLL Slave Mode (PLL Reference Clock: BICK pin) (x=1 to 4)
MS1402-E-06
2013/02
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