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AK4679 参数 Datasheet PDF下载

AK4679图片预览
型号: AK4679
PDF下载: 下载PDF文件 查看货源
内容描述: 24位立体声编解码器与DSP和MIC / RCV / HP / SPK / LINE- AMP [24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP]
分类和应用: 解码器编解码器
文件页数/大小: 220 页 / 2080 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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[AK4679]  
PLL Mode (PMPLL bit = “1”) (Audio I/F)  
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates clock that is selected by the PLL3-0  
and FS3-0 bits. The PLL lock time is shown in Table 5. This lock time is when the audio I/F is supplied stable clocks after  
PLL is powered-up (PMPLL bit = “0” “1”) or when the sampling frequency changes.  
1) Setting of PLL Mode  
PLL Lock  
PLL3  
bit  
PLL2  
bit  
PLL1  
bit  
PLL0  
bit  
PLL Reference  
Clock Input Pin  
Input  
Frequency  
Mode  
Time  
(max)  
2ms  
2
3
4
5
6
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
BICK pin  
BICK pin  
MCKI pin  
MCKI pin  
MCKI pin  
MCKI pin  
MCKI pin  
MCKI pin  
MCKI pin  
MCKI pin  
MCKI pin  
MCKI pin  
32fs  
64fs  
2ms  
11.2896MHz  
12.288MHz  
12MHz  
24MHz  
19.2MHz  
13MHz  
26MHz  
13.5MHz  
27MHz  
25MHz  
N/A  
10ms  
10ms  
10ms  
10ms  
10ms  
10ms  
10ms  
10ms  
10ms  
10ms  
(default)  
7
8
10  
11  
12  
13  
14  
Others  
0
1
1
1
Others  
Table 5. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available)  
2) Setting of sampling frequency in PLL Mode  
When PLL reference clock input is MCKI and BICK pins, the sampling frequency is selected by FS3-0 bits as defined in  
Table 6.  
Sampling Frequency (Note  
Mode  
FS3 bit  
FS2 bit  
FS1 bit  
FS0 bit  
74)  
0
1
2
3
5
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
0
0
1
0
0
1
1
0
1
1
1
1
0
1
0
1
1
1
0
1
1
8kHz mode  
12kHz mode  
16kHz mode  
24kHz mode  
11.025kHz mode  
22.05kHz mode  
32kHz mode  
48kHz mode  
44.1kHz mode  
N/A  
7
10  
11  
15  
Others  
(default)  
Others  
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (N/A: Not available)  
Note 74. When the MCKI pin is the PLL reference clock input, the sampling frequency generated by PLL differs from the  
sampling frequency of mode name in some combinations of MCKI frequency(PLL3-0 bits) and sampling  
frequency (FS3-0 bits). Refer to Table 7 for the details of sampling frequency. In master mode, LRCK and BICK  
output frequency correspond to sampling frequencies shown in Table 7. When the BICK pin is the PLL reference  
clock input, the sampling frequency generated by PLL is the same sampling frequency of mode name.  
MS1402-E-06  
2013/02  
- 48 -  
 
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