[AK4679]
■ Headphone-Amp Output
Example :
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
HP Volume Level: −6dB
5 band EQ: Enable
FS3-0 bits
0000
1111
(Addr:03H, D7-4)
(1)
(1) Addr:03H, Data FxH
(2) Addr:0FH, Data 20H
(3) Addr:17H, Data 0AH
(4) Addr:01H, Data 0DH
(5) Addr:0BH, Data 03H
Playback
(2)
HPG5-0 bits
23H
0
20H
1
(Addr:0FH, D5-0)
(3)
(8)
5EQ bit
(Addr:17H, D3)
0
PMDAL/R bits
PMEQ bit
(Addr:01H, D3-2, D0)
(4)
(7)
(5)
PMHPL/R bits
(Addr:0BH, D1-0)
28ms
(6)
HPL/R pins
0V
Normal Output
0V
(6) Addr:0BH, Data 00H
(7) Addr:01H, Data 00H
(8) Addr:17H, Data 02H
Figure 154. Headphone-Amp Output Sequence
(Headphone Playback: SDTI → Audio I/F → 5-band EQ → DATT-A → DACL/R → HPL/HPR)
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). DAC and Headphone-Amp should be powered-up in consideration
of VCOM rise time and PLL lock time after a sampling frequency is changed when the AK4679 is in PLL
mode.
(2) Set up analog volume for HP-Amp (Addr: 0FH, HPG5-0 bits)
(3) Enable 5-band Equalizer: 5EQ bit = “0” Æ “1” (Frequency Response and gain are selected by Addr =
50H-6EH.)
(4) Power up DAC and EQ : PMDAL = PMDAR = PMEQ bits = “0” → “1”
(5) Power up Headphone-Amp and charge pump circuit: PMHPL = PMHPR bits = “0” → “1”
The power-up time of HP-Amp block is 28ms. HPL and HPR pins output 0V until the power-up time of
HP-Amp block passes.
(6) Power down Headphone-Amp and charge pump circuit: PMHPL = PMHPR bits = “1” → “0”
HPL and HPR pins go to 0V.
(7) Power down DAC and EQ: PMDAL = PMDAR = PMEQ bits = “1” → “0”
(8) Disable 5-band Equalizer: 5EQ bit = “1” Æ “0”
MS1402-E-06
2013/02
- 210 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
