[AK4679]
■ Stereo Line Output
Example:
PLL, Master Mode
FS3-0 bits
0000
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
OVOLC bit = “1”(default)
Digital Volume Level: −8dB
LINEOUT Volume Level: −3dB
1111
010
(Addr:03H, D7-4)
(1)
LVL2-0 bits
011
(Addr:0EH, D2-0)
(1) Addr:03H, Data:FxH
(2)
(2) Addr:0EH, Data:02H
Addr:19H, Data:03H
Addr:14H, Data:05H
Addr:09H, Data:03H
PFSEL bis
(Addr:19H, D0)
PFMXL/R1-0 bits
0000
0101
(Addr:14H, D3-0)
(3) Addr:1DH&1EH, Data:1CH
(4) Addr:0AH, Data:04H
DACL/R bits
(Addr:09H, D1-0)
(9)
(5) Addr:01H, Data:0CH
Addr:00H, Data:03H
Addr:0AH, Data:07H
OVL/R6-0 bits
0CH
1CH
(Addr:1DH&1EH, D6-0)
(3)
LOPS bit
(6) Addr:0AH, Data:03H
Playback
(Addr:0AH, D2)
(4)
(6)
(7)
(10)
PMDAL/R bits
PMPFIL bit
(Addr:00H, D7-6, D1)
(7) Addr:0AH, Data:07H
(5)
(8)
PML/RO bits
(8) Addr:0AH, Data:04H
Addr:00H, Data:01H
Addr:01H, Data:00H
(Addr:0AH, D1-0)
>300 ms
>300 ms
LOUT pin
ROUT pin
Normal Output
(9) Addr:09H, Data:00H
(10) Addr:0AH, Data:00H
Figure 156. Stereo Lineout Sequence
(Lineout Playback: SDTI → Audio I/F → SVOLA → DATT-A → DACL/R → LOUT/ROUT)
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up the sampling frequency (FS3-0 bits). DAC and Stereo Line-Amp should be powered-up in consideration
of VCOM rise time and PLL lock time after the sampling frequency is changed when the AK4679 is in PLL
mode.
(2) Set up the path of “SDTI Æ DAC Æ Stereo Line-Amp”: PFSEL = “0” Æ “1”, PFMXL1-0 = PFMXR1-0 bits =
“0000” Æ “0101”, DACL = DACR bits = “0” Æ “1”
Set up analog volume for Stereo Line-Amp (Addr: 0EH, LVL2-0 bits)
(3) Set up the output digital volume (Addr: 1DH and 1EH)
When OVOLC bit is “1” (default), OVL6-0 bits (1DH) set the volume of both channels. After DAC is
powered-up, the digital volume changes from default value (0dB) to the register setting value by the soft
transition.
(4) Enter power-save mode of Stereo Line-Amp: LOPS bit = “0” Æ “1”
(5) Power-up DAC, Programmable Filter and Stereo Line-Amp: PMDAL = PMDAR = PMPFIL = PMLO =
PMRO bits = “0” → “1”
LOUT and ROUT pins rise up to VCOM voltage after PMLO and PMRO bits are changed to “1”. Rise time is
300ms (max.) at C=1μF and AVDD=1.8V.
(6) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1” Æ “0”
LOPS bit should be set to “0” after LOUT and ROUT pins rise up. Stereo Line-Amp goes to normal operation
by setting LOPS bit to “0”.
(7) Enter power-save mode of Stereo Line-Amp: LOPS bit: “0” Æ “1”
(8) Power-down DAC, Programmable Filter and Stereo Line-Amp: PMDAL = PMDAR = PMPFIL = PMLO =
PMRO bits = “1” → “0”
LOUT and ROUT pins fall down to VSS1. Fall time is 300ms(max.) at C=1μF and AVDD=1.8V.
(9) Disable the path of “DAC Æ Stereo Line-Amp”: DACL = DACR bits = “1” Æ “0”
(10)Exit power-save mode of Stereo Line-Amp: LOPS bit = “1” Æ “0”
LOPS bit should be set to “0” after LOUT and ROUT pins fall down.
MS1402-E-06
2013/02
- 212 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
