[AK4679]
■ Stop of Clock
1. PLL Master Mode
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
Sampling Frequency: 44.1kHz
(1)
PMPLL bit
(Addr:04H, D0)
External MCKI
Input
(1) Addr:04H, Data:02H
(2)
(2) Stop an external MCKI
Figure 157. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop an external MCKI clock.
2. PLL Slave Mode (BICK pin)
Example
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
(1)
PMPLL bit
(Addr:04H, D0)
Sampling Frequency: 44.1kHz
(2)
External BICK
External LRCK
Input
Input
(1) Addr:04H, Data:00H
(2)
(2) Stop the external clocks
Figure 158. Clock Stopping Sequence (2)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external BICK and LRCK clocks.
MS1402-E-06
2013/02
- 213 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
