[AK4679]
■ Speaker-Amp Output
Example :
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
SPK Volume Level: −9dB
5 band EQ: Enable
FS3-0 bits
0000
1111
1000
(Addr:03H, D7-4)
(1)
(1) Addr:03H, Data FxH
(2) Addr:10H, Data B8H
(3) Addr:09H, Data C0H
(4) Addr:17H, Data 0AH
(5) Addr:01H, Data 0DH
(6) Addr:0DH, Data 08H
Playback
(2)
SPKG3-0 bits
(Addr:10H, D3-0)
1011
(3)
(10)
DACSL/R bits
(Addr:09H, D7-6)
(4)
(9)
5EQ bit
(Addr:17H, D3)
0
1
0
PMDAL/R bits
PMEQ bit
(Addr:01H, D3-2, D0)
(5)
(8)
(6)
PMSPK bit
(Addr:0DH, D4)
32ms
(7)
SPP/SPN pins
Hi-Z
0V Normal Output
Hi-Z
(7) Addr:0DH, Data 00H
(8) Addr:01H, Data 00H
(9) Addr:17H, Data 02H
(10) Addr:09H, Data 00H
Figure 155. Speaker-Amp Output Sequence
(Headphone Playback: SDTI → Audio I/F → 5-band EQ → DATT-A → DACL/R → SPP/SPN)
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). DAC and Speaker-Amp should be powered-up in consideration of
VCOM rise time and PLL lock time after a sampling frequency is changed when the AK4679 is in PLL mode.
(2) Set up analog volume for SPK-Amp (Addr: 10H, SPKG3-0 bits)
(3) Set up the path of “SDTI Æ DAC Æ SPK-Amp”: DACSL = DACSR bits = “0” → “1”
(4) Enable 5-band Equalizer: 5EQ bit = “0” Æ “1” (Frequency Response and gain are selected by Addr =
50H-6EH.)
(5) Power up DAC and EQ: PMDAL = PMDAR = PMEQ bits = “0” → “1”
(6) Power up SP-Amp block: PMSPK bit = “0” → “1”
The power-up time of SPK-Amp block is 32ms. SPP and SPN pins output 0V until the power-up time of
SPK-Amp block passes.
(7) Power down SPK-Amp block: PMSPK bit = “1” → “0”
SPN and SPP pins go to 0V.
(8) Power down DAC and EQ: PMDAL = PMDAR = PMEQ bits = “1” → “0”
(9) Disable 5-band Equalizer: 5EQ bit = “1” Æ “0”
(10)Disable the path of “DAC → Speaker-Amp”: DACSL = DACSR bits = “1” → “0”
MS1402-E-06
2013/02
- 211 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
