[AK4492]
(2)-4. Power-down/up sequence in FS Auto Detect Mode when using internal LDO.
Power
(2)
PDN pin
DVDD pin
(3)
Internal PDN
Internal
Normal Operation (Register Write and DAC Operation are Available)
State
AFSD bit
AFSD bit = “0”
AFSD bit = “0”
AFSD bit = “1”
(4)
Power up
Internal OSC
Don’t care
Clock In
MCLK, BICK, LRCK
(1)
Fs Auto Detect mode Enable
(5)
(6)
Internal FS Auto Detect Circuit
Figure 24. Power-down/up Sequence at FS AutoDetect Mode
Note:
(1) Do not input a clock when power supplies are powered down.
(2) The PDN pin must be held “L” for more than 150ns after turning on AVDD, TVDD and VDDL/R.
(3) When the LDOE pin = “H”, the internal LDO starts operation after power up. The internal circuit
will be powered up after the shutdown switch is ON (max. 2ms) following the internal oscillator
count up.
When the LDOE pin = “L”, the internal shutdown switch is ON. The internal circuit will be powered
up after the shutdown switch is ON (max. 1ms).
(4) When AFSD bit = “1”, the internal oscillator starts operation. It takes10 us (max) until the
oscillation frequency is stabled.
(5) After AFSD bit = “1”, Fs Auto Detect Mode is started in 8/fs~9/fs.
(6) After AFSD bit = “0”, the Fs Auto Detect ciruit stops internal operation and the OSC is stopped.
016011073-E-00
2016/12
- 46 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
