[AK4492]
[3] External Digital Filter Mode (EXDF Mode)
The external clocks that are required in EXDF mode are MCLK, BCK and WCK. The BCK and MCLK
clocks must be the same frequency and must not burst. BCK and MCLK frequencies for each sampling
speed are shown in Table 23. ECS bit selects WCK frequency from 384kHz and 768kHz. DW indicates
the number of BCK in one WCK cycle.
All circuits except the internal LDO are automatically placed in power-down state when MCLK edge is not
detected for more than 1us during a normal operation (PDN pin =“H”), and the analog output becomes
Hi-Z state. The power-down state is released and the AK4492 starts operation by inputting MCLK again.
In this case, register settings are not initialized.
When the reset is released (PDN pin = “L” → “H”), the AK4492 is in power-down state until MCLK, BCK
and WCK are input.
Table 23. System Clock Example (EXDF Mode)
MCLK&BCK [MHz]
Sampling
Speed[kHz]
WCK ECS
128fs
N/A
192fs
N/A
256fs
N/A
384fs
N/A
512fs
768fs
22.5792 33.8688 16fs
44.1(30~48)
44.1(30~48)
0
1
(default)
32
N/A
48
33.8688
96
DW
8fs
DW
8fs
N/A
N/A
N/A
N/A
11.2896 16.9344
32
24.576
32
48
36.864
48
N/A
N/A
N/A
N/A
N/A
96(54~96)
96(54~96)
0
1
0
1
DW
4fs
DW
4fs
12.288
32
18.432
48
N/A
36.864
96
N/A
N/A
N/A
24.576
32
N/A
36.864
48
36.864
96
N/A
N/A
N/A
192(108~192)
192(108~192)
DW
2fs
DW
N/A
016011073-E-00
2016/12
- 48 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
