[AK4492]
(2)-3. Sampling Frequency (FS) Auto Detect Mode (AFSD bi = “1”)
MCLK frequency and the sampling rate is detected automatically (Table 14). In this mode, DFS[2:0] bits
and ACKS bit settings are invalid. The MCLK frequency corresponding to each sampling speed should
be provided externally (Table 18, Table 19). Internal operation sequence in FS auto detect mode is
shown in Figure 24.
Table 18. System Clock Example 1 @PCM Mode
LRCK
fs
MCLK(MHz)
Sampling
Speed
16fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
32fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
12.288
24.576
48fs
N/A
N/A
64fs
N/A
N/A
96fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
36.864
N/A
128fs
N/A
N/A
N/A
N/A
32.0 kHz
44.1 kHz
48.0 kHz
88.2 kHz
96.0 kHz
176.4 kHz
192.0 kHz
384 kHz
768 kHz
Normal
N/A
N/A
N/A
N/A
Double
Quad
N/A
N/A
N/A
N/A
N/A
22.5792
24.5760
N/A
N/A
N/A
18.432
36.864
24.576
49.152
Oct
Hex
12.288
N/A
(N/A: Not available)
Table 19. System Clock Example 2 @PCM Mode
MCLK (MHz)
LRCK
fs
Sampling
Speed
192fs
256fs
384fs
512fs
768fs
1024fs
1152fs
32.0 kHz
44.1 kHz
48.0 kHz
88.2 kHz
96.0 kHz
176.4 kHz 33.8688 45.1584
192.0 kHz 36.8640 49.1520
384 kHz
768 kHz
N/A
N/A
N/A
N/A
N/A
8.1920 12.2880 16.3840 24.5760 32.768 36.8640
11.2896 16.9344 22.5792 33.8688
12.2880 18.4320 24.5760 36.8640
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Normal
22.5792 33.8688 45.1584
24.5760 36.8640 49.1520
N/A
N/A
N/A
N/A
N/A
N/A
Double
Quad
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Oct
Hex
(N/A: Not available)
016011073-E-00
2016/12
- 45 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
