[AK4492]
Table 9. System Clock Example 2 (Auto Setting Mode @Pin Control Mode)
MCLK (MHz)
LRCK
Fs
Sampling
Speed
256fs
8.1920
11.2896
12.2880
22.5792
24.5760
N/A
384fs
12.2880
16.9344
18.4320
33.8688
36.8640
N/A
512fs
16.3840
22.5792
24.5760
N/A
768fs
24.5760
33.8688
36.8640
N/A
1024fs
32.7680
N/A
1152fs
36.8640
N/A
32.0 kHz
44.1 kHz
48.0 kHz
88.2 kHz
96.0 kHz
176.4 kHz
192.0 kHz
384 kHz
768 kHz
Normal
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Double
Quad
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Oct
Hex
N/A
N/A
N/A
N/A
N/A
N/A
(N/A: Not available)
When MCLK= 256fs/384fs, auto setting mode supports sampling rate of 8kHz~96kHz (Table 10).
However, the DR and S/N performances will degrade approximately 3dB as compared to when MCLK =
256fs/384fs for DR and MCLK= 512fs/768fs for S/N, respectively if the sampling rate is under 54kHz.
Table 10. DR and S/N Relationship with MCLK Frequency (fs = 44.1kHz)
ACKS pin
MCLK
256fs/384fs/512fs/768fs
256fs/384fs
DR, S/N
123 dB
120 dB
123 dB
L
H
H
512fs/768fs
Note 47. This Characteristic is supported by using External Circuit (Figure 74)
016011073-E-00
2016/12
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AKM [ ASAHI KASEI MICROSYSTEMS ]
