[AK4492]
[2] DSD Mode
The AK4492 has a DSD playback function. The external clocks that are required in DSD mode are MCLK
and DCLK. MCLK should be synchronized with DCLK but the phase is not critical. The frequency of
MCLK is set by DCKS bit (Table 20).
The AK4492 is automatically placed in power-down state when MCLK is stopped during a normal
operation (PDN pin =“H”), and the analog output becomes Hi-z state. When the reset is released (PDN
pin = “L” → “H”), the AK4492 is in power-down state until MCLK and DCLK are input.
Table 20. System Clock (DSD Mode, fs = 32 kHz, 44.1 kHz, 48 kHz)
DCKS bit MCLK Frequency DCLK Frequency
0
1
512fs
768fs
64fs/128fs/256fs (default)
64fs/128fs/256fs
The AK4492 supports DSD data stream of 2.8224MHz (64fs), 5.6448MHz (128fs) and 11.2896MHz
(256fs). The data sampling speed is selected by DSDSEL[1:0] bits (Table 21).
Table 21. DSD Data Stream Select
DSD data stream
DSDSEL1 DSDSEL0
fs = 32 kHz
2.048 MHz
4.096 MHz
8.192 MHz
N/A
fs = 44.1 kHz
2.8224 MHz
5.6448 MHz
11.2896 MHz
N/A
fs = 48 kHz
3.072 MHz
6.144 MHz
12.288 MHz
N/A
0
0
1
1
0
1
0
1
(default)
The AK4492 has a Volume bypass function for play backing DSD signal. Two modes are selectable by
DSDD bit (Table 22). When setting DSDD bit = “1”, the output volume control and zero detect functions
are not available.
Table 22. DSD Playback Path Select
DSDD
Mode
0
1
Normal Path
Volume Bypass
(default)
016011073-E-00
2016/12
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AKM [ ASAHI KASEI MICROSYSTEMS ]
