[AK4492]
(2) Register Control Mode (PSN pin = “L”)
(2)-1. Manual Setting Mode (AFSD bit = “0”, ACKS bit = “0”)
MCLK frequency is detected automatically and the sampling speed is set by DFS[2:0] bits (Table 11). The
MCLK frequency corresponding to each sampling speed that should be provided externally (Table 12,
Table 13). The AK4492 is set to Manual Setting Mode at power-up (PDN pin = “L” →“H”). When DFS2-0
bits are changed, the AK4492 should be reset by RSTN bit.
Table 11. Sampling Speed (Manual Setting Mode @Register Control Mode)
DFS2
bit
DFS1
bit
DFS0
bit
Sampling Rate (fs)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Normal Speed Mode
(default)
8 kHz 54 kHz
54 kHz 108 kHz
120 kHz 216 kHz
120 kHz 216 kHz
384 kHz
Double Speed Mode
Quad Speed Mode
Quad Speed Mode
Oct Speed Mode
Hex Speed Mode
Oct Speed Mode
Hex Speed Mode
768 kHz
384 kHz
768 kHz
Table 12. System Clock Example 1 (Manual Setting Mode @Register Control Mode)
LRCK
Fs
MCLK (MHz)
Sampling
Speed
16fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
32fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
12.288
24.576
48fs
N/A
N/A
64fs
N/A
N/A
96fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
36.864
N/A
128fs
N/A
N/A
N/A
N/A
32.0 kHz
44.1 kHz
48.0 kHz
88.2 kHz
96.0 kHz
176.4 kHz
192.0 kHz
384 kHz
768 kHz
Normal
N/A
N/A
N/A
N/A
Double
Quad
N/A
N/A
N/A
N/A
N/A
22.5792
24.5760
N/A
N/A
N/A
18.432
36.864
24.576
49.152
Oct
Hex
12.288
N/A
(N/A: Not available)
Table 13. System Clock Example 2 (Manual Setting Mode @Register Control Mode)
LRCK
fs
MCLK (MHz)
512fs
Sampling
Speed
192fs
N/A
N/A
N/A
N/A
N/A
256fs
384fs
768fs
1024fs
1152fs
32.0 kHz
44.1 kHz
48.0 kHz
88.2 kHz
96.0 kHz
176.4 kHz 33.8688 45.1584
192.0 kHz 36.8640 49.1520
384 kHz
768 kHz
8.1920 12.2880 16.3840 24.5760 32.7680 36.8640
11.2896 16.9344 22.5792 33.8688
12.2880 18.4320 24.5760 36.8640
22.5792 33.8688 45.1584
24.5760 36.8640 49.1520
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Normal
N/A
N/A
N/A
N/A
N/A
N/A
Double
Quad
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Oct
Hex
(N/A: Not available)
016011073-E-00
2016/12
- 43 -