欢迎访问ic37.com |
会员登录 免费注册
发布采购

AK4492ECB 参数 Datasheet PDF下载

AK4492ECB图片预览
型号: AK4492ECB
PDF下载: 下载PDF文件 查看货源
内容描述: [Quality Oriented 32-Bit 2ch DAC]
分类和应用:
文件页数/大小: 101 页 / 2100 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
 浏览型号AK4492ECB的Datasheet PDF文件第46页浏览型号AK4492ECB的Datasheet PDF文件第47页浏览型号AK4492ECB的Datasheet PDF文件第48页浏览型号AK4492ECB的Datasheet PDF文件第49页浏览型号AK4492ECB的Datasheet PDF文件第51页浏览型号AK4492ECB的Datasheet PDF文件第52页浏览型号AK4492ECB的Datasheet PDF文件第53页浏览型号AK4492ECB的Datasheet PDF文件第54页  
[AK4492]  
Figure  
Table 24. Audio Interface Format  
TDM1 TDM0 DIF2 DIF1 DIF0  
LR  
CK  
Mode  
SDATA Format  
BICK  
bit  
bit  
bit  
bit  
bit  
0
1
2
0
0
0
0
0
1
0
1
0
16-bit LSB justified  
20-bit LSB justified  
24-bit MSB justified  
16-bit I2S Compatible  
24-bit I2S Compatible  
24-bit LSB justified  
32-bit LSB justified  
32-bit MSB justified  
32-bit I2S Compatible  
N/A  
H/L  
H/L  
H/L  
L/H  
Figure 25  
Figure 26  
Figure 27  
32fs  
40fs  
48fs  
32fs  
3
0
1
1
Figure 28  
Normal  
(Note 49)  
L/H  
0
0
48fs  
4
5
6
7
-
1
1
1
1
-
0
0
1
1
-
0
1
0
1
-
H/L  
H/L  
H/L  
L/H  
-
Figure 26  
Figure 29  
Figure 30  
Figure 31  
-
48fs  
64fs  
64fs  
64fs  
-
-
-
-
-
N/A  
-
-
-
8
9
0
0
1
1
1
1
-
1
1
0
0
1
1
-
0
1
0
1
0
1
-
24-bit MSB justified  
24-bit I2S Compatible  
H/L 128fs  
L/H 128fs  
H/L 128fs  
H/L 128fs  
H/L 128fs  
L/H 128fs  
Figure 32  
Figure 33  
Figure 34  
Figure 32  
Figure 32  
Figure 33  
-
TDM128  
TDM256  
TDM512  
0
1
1
1
0
1
10  
11  
12  
13  
-
24-bit LSB justified  
32-bit LSB justified  
32-bit MSB justified  
32-bit I2S Compatible  
N/A  
-
-
-
-
-
-
-
-
N/A  
-
14  
15  
16  
17  
18  
19  
-
0
0
1
1
1
1
-
1
1
0
0
1
1
-
0
1
0
1
0
1
-
24-bit MSB justified  
24-bit I2S Compatible  
24-bit LSB justified  
32-bit LSB justified  
32-bit MSB justified  
32-bit I2S Compatible  
N/A  
H/L 256fs  
L/H 256fs  
H/L 256fs  
H/L 256fs  
H/L 256fs  
L/H 256fs  
Figure 35  
Figure 36  
Figure 37  
Figure 35  
Figure 35  
Figure 36  
-
-
-
-
-
-
-
-
-
N/A  
-
20  
21  
22  
23  
24  
25  
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
24-bit MSB justified  
24-bit I2S Compatible  
24-bit LSB justified  
32-bit LSB justified  
32-bit MSB justified  
32-bit I2S Compatible  
H/L 512fs  
L/H 512fs  
H/L 512fs  
H/L 512fs  
H/L 512fs  
L/H 512fs  
Figure 38  
Figure 39  
Figure 40  
Figure 38  
Figure 38  
Figure 39  
Note 49. BICK more than setting bit must be input to each channel. In the LRCK column, H/Lindicates  
that L channel data can be input when LRCK is Hand R channel data can be input when LRCK  
is L. L/Hindicates L channel data can be input when LRCK is Land R channel data can be  
input when LRCK is H.  
Note 50. The default settings in Register Control Mode are shown below.  
TDM1 bit = “0”, TDM0 bit = “0”, DIF2 bit = “1”, DIF1 bit = “1”, DIF0 bit = “0”  
016011073-E-00  
2016/12  
- 50 -  
 
 
 复制成功!