[AK4492]
(1) Pin Control Mode (PSN pin = “H”)
(1)-1. Manual Setting Mode (ACKS pin = “L”)
The MCLK frequency corresponding to each sampling speed should be provided externally (Table 6).
DFS1-0 bits are fixed to “00”. In this mode, quad speed and double speed modes are not available.
Table 6. System Clock Example (Manual Setting Mode @Pin Control Mode)
LRCK
fs
MCLK (MHz)
384fs 512fs
BICK
64fs
128fs 192fs
256fs
768fs
1024fs
1152fs
32.0 kHz N/A
44.1 kHz N/A
48.0 kHz N/A
(N/A: Not available)
N/A
8.1920 12.2880 16.3840 24.5760 32.7680 36.8640 2.0480 MHz
N/A 11.2896 16.9344 22.5792 33.8688
N/A 12.2880 18.4320 24.5760 36.8640
N/A
N/A
N/A
N/A
2.8224 MHz
3.0720 MHz
(1)-2. Auto Setting Mode (ACKS pin = “H”)
In auto setting mode, MCLK frequency and sampling frequency are detected automatically (Table 7).
MCLK of corresponded frequency to each sampling speed mode should be input externally (Table 8,
Table 9).
Table 7. Sampling Speed (Auto Setting Mode @Pin Control Mode)
MCLK
Sampling Speed
1152fs/1024fs
Normal (fs 32 kHz)
512fs/256fs 768fs/384fs
Normal
Double
Quad
Oct
256fs
128fs
64fs
384fs
192fs
96fs
32fs
48fs
Hex
Table 8. System Clock Example 1 (Auto Setting Mode @Pin Control Mode)
MCLK (MHz)
LRCK
Fs
Sampling
Speed
32fs
48fs
64fs
96fs
128fs
192fs
32.0 kHz
44.1 kHz
48.0 kHz
88.2 kHz
96.0 kHz
176.4 kHz
192.0 kHz
384 kHz
768 kHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
24.576
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
36.864
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Normal
Double
Quad
N/A
N/A
22.5792
24.5760
N/A
33.8688
36.8640
N/A
Oct
Hex
24.576
36.864
N/A
N/A
(N/A: Not available)
016011073-E-00
2016/12
- 41 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
