Ambassador T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
Advance Data Sheet
November 1999
4 Electrical Characteristics (continued)
4.8 H-Bus Timing (Extract from H.100 Spec., Rev. 1.0)
4.8.1 Clock Alignment
FRAME BOUNDARY
/CT_FRAME (A/B)
CT_C8 (A/B)
/FR_COMP
/C16
C2
/C4
SCLK
(2.048 MHz)
SCLKX2
(2.048 MHz MODE)
SCLK
(4.096 MHz MODE)
SCLKX2
(4.096 MHz MODE)
SCLK
(8.192 MHz MODE)
SCLKX2
(8.192 MHz MODE)
5-6119F
Figure 24. Clock Alignment
4.8.2 Frame Diagram
FRAME BOUNDARY
125 µs
/CT_FRAME
CT_C8
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
CT_DX
TIME
SLOT
0
127
5-6120F
Note: Bit 1 is the MSB. Bit 8 is the LSB. MSB is always transmitted first in all transfers.
Figure 25. Frame Diagram
Lucent Technologies Inc.
85
AGERE [ AGERE SYSTEMS ]
