Ambassador T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
Advance Data Sheet
November 1999
3.1.3 Power-On Reset
3 Using the TSI Devices
No power-on reset is available. It is expected that the
host microprocessor or applications board will provide
an external control to the RESET pin for performing a
hardware reset. The PLLs must not be enabled prior to
3.1 Resets
3.1.1 Hardware Reset
establishing a stable supply voltage. There are two
methods to accomplish this:
A hardware reset utilizes the (active-low) RESET pin.
On activation, it immediately places all outputs into
3-state. Individual output sections must be re-enabled
by setting the appropriate bits high in the MCR register.
Internally, the local memory (T8100A, T8105 only) is in
an undefined state, all CAM empty bits are set, all state
machines are reset, and all registers are cleared to
zero.
■ Tie the En1 and En2 pins to the same line that drives
the RESET, which forces the PLLs into an off condi-
tion while the devices reset asynchronously.
■ Add external capacitors from En1 to ground and from
En2 to ground. (The values of the capacitors should
be 1 µF or greater.) The capacitors will form RC cir-
cuits with the En1 and En2 internal pull-ups and will
charge up to enable the PLLs after several millisec-
onds. The RC circuit affects the power-on reset for
the PLLs. The long rise time provides some delay.
3.1.2 Software Reset
This is accomplished by setting the MSB of the master
control and status register (see Section 2.1.2 Master
Control and Status Register). The local and H-bus con-
nections are rendered invalid, all registers are cleared
except MCR, CLKERR1, CLKERR2, CLKERR3, and
SYSERR (these registers are cleared with separate
MCR control bits); the state machines are also reset.
Writing the value 0xE0 to the MCR is a full software
reset. Writing 0x0E enables all pin groups (though indi-
vidual pins still require setup). This soft reset is clocked
by the crystal.
Lucent Technologies Inc.
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