Ambassador T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
Advance Data Sheet
November 1999
2 Architecture and Functional Description (continued)
Figure 3 shows a block diagram of the TSI devices. The devices operate on a 3.3 V supply for both the core and
I/Os, though the I/Os are TTL compatible and 5 V tolerant.
H.100, H.110, H-MVIP, MVIP, SC-BUS
S/P AND P/S CONVERTERS
512*
LOCATION
DATA
SRAM
THREE 512*
LOCATION
CONNECTION
CAMs
†
INPUT
LOGIC
AND S/P
CONVERT
1024
OUTPUT
LOGIC
AND P/S
CONVERT
LOCAL IN
LOCAL OUT
LOCATION
DATA
MEMORY
†
1024
LOCATION
CONNECTION
MEMORY
INTERNAL
DATA
INTERNAL
ADDRESS
AND
CONTROL
INTERNAL
CLOCKS AND
STATE
COUNTER
ADDR[1:0]
FRAME GROUP
INTERFACE
LOGIC
MICROPROCESSOR
INTERFACE
TIMING AND
CONTROL
FRAME
GROUPS
DATA[7:0]
…
…
…
µP CONTROLS
MISC. I/O
CLOCKS AND REFS
5-6101.a (F)
* For T8100 and T8100A, there are only 256 locations.
† T8102 does not have local data memory.
Figure 3. Block Diagram of the TSI Devices
14
Lucent Technologies Inc.
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