Ambassador T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
Advance Data Sheet
November 1999
With the advent of the H.100 bus specification by the
Enterprise Computer Telephony Forum, the computer-
telephony industry has agreed on a single telecom bus
for use with PCI and compact PCI computers. H.100
facilitates interoperation of components, thus providing
maximum flexibility to equipment manufacturers, value-
1 Product Overview (continued)
1.10 Interfaces
1.10.1 Microprocessors
The devices provide the user a choice of either Motor-
ola or Intel interfacing through an 8-bit data bus, a 2-bit
address bus, and multifunction control pins. All access
to the devices’ memory blocks and registers use indi-
rect addressing.
added resellers, system integrators, and others build-
ing computer-based telecommunications applications.
2 Architecture and Functional
Description
1.10.2 Framing Groups
Two groups of programmable framing signals are avail-
able. Each group is composed of 12 sequenced lines
operating in one of four modes. The devices support
1-bit, 2-bit, 1-byte, and 2-byte pulse widths. Starting
position of the pulse sequences are also programma-
ble.
The devices are H.100-compliant and provide a com-
plete interface between the H.100 bus and a wide vari-
ety of telephony interface components, processors,
and other circuits. The bus interface provides all signals
needed for the H.100 bus, the H-MVIP and MVIP-90
buses, or the SC-Bus. Local interfaces include 16 serial
inputs and 16 serial outputs based on the Lucent Tech-
nologies Microelectronics Group concentration high-
way interface (CHI). The T8100A and the T8105
include two built-in time-slot interchangers. The first
provides a local switching domain with up to 1024 pro-
grammable connections between time slots on the local
CHI inputs and outputs. The second provides program-
mable connections between any time slot on the H.100
bus and any time slot in the local switching domain.
The T8105 has 512 programmable connections while
the T8100A has 256. The T8102 has only 1 TSI for
switching up to 512 programmable connections on the
H.100 bus and any time slot in the local switching
domain. All Ambassador devices are configured via a
microprocessor interface. This interface can also read
and write time slot and device data. Onboard clock cir-
cuitry, including a DPLL, supports all H.100 clock
modes including MVIP and SC-Bus compatibility
clocks. The local CHI interfaces support PCM rates of
2.048 Mbits/s, 4.096 Mbits/s, and 8.192 Mbits/s. Each
device has internal circuitry to support either minimum
latency or multi-time-slot frame integrity. Frame integrity
is a requisite feature for applications that switch wide-
band data (ISDN H-channels). Minimum latency is
advantageous in voice applications.
1.10.3 General-Purpose Register and I/O
A general-purpose, 8-bit, input/output port is provided
as either byte-wide I/O or bit addressed I/O.
1.11 Applications
■ Computer-telephony systems
■ Enhanced service platforms
■ WAN access devices
■ PBXs
■ Wireless base stations
1.12 Application Overview
The integration of computers and telecommunications
has enabled a wide range of new communications
applications and has fueled an enormous growth in
communications markets. A key element in the devel-
opment of computer-based communications equipment
has been the addition of an auxiliary telecom bus to
existing computer systems. Most manufacturers of
high-capacity, computer-based telecommunications
equipment have incorporated some such telecom
bus in their systems. Typically, these buses and bus
interfaces are designed to transport and switch
N x 64 kbits/s low-latency telecom traffic between
boards within the computer, independent of the com-
puter’s I/O and memory buses. At least a half dozen of
these PC-based telecom buses emerged in the early
1990s for use within equipment based on ISA/EISA
and MCA computers.
All three TSIs have the following four major sections:
■ Local bus—refers to the local streams.
■ H-bus—refers to the H.100/H.110/H-MVIP and
legacy streams.
■ Interface—refers to the microprocessor interface,
frame groups, and general-purpose I/O (GPIO).
■ Timing—the rate multipliers, DPLL, and clocking
functions.
Lucent Technologies Inc.
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AGERE [ AGERE SYSTEMS ]
