AD7366/AD7367
SERIAL INTERFACE
CS
On the rising edge of
D
, the conversion is terminated and
CS
Figure 2± and Figure 26 show the detailed timing diagram
for serial interfacing to the AD7366 and the AD7367. On the
OUTA and DOUTB go back into three-state. If
high, but is instead held low for a further 12 SCLK cycles for the
AD7366 or 14 SCLK cycles for the AD7367, on either DOUTA or
OUTB, the data from the other ADC follows on the DOUT pin.
This is illustrated in Figure 27 and Figure 28 where the case for
OUTA is shown. In this case, the DOUT line in use goes back into
three-state on the rising edge of
is not brought
CNꢁST
falling edge of
converts the selected channels. These conversions are performed
CNꢁST
the AD7366/AD7367 simultaneously
D
using the on-chip oscillator. After the falling edge of
the BUSY signal goes high, indicating the conversion has started.
It returns low once the conversion has been completed. The data
can now be read from the DOUT pins.
D
CS
.
If the falling edge of SCLK coincides with the falling edge of
CS
CS
and SCLK signals are required to transfer data from the
, then the falling edge of SCLK is not acknowledged by the
AD7366/AD7367, and the next falling edge of the SCLK is the
CS
AD7366/AD7367. The AD7366/AD7367 have two output pins
corresponding to each ADC. Data can be read from the AD7366/
AD7367 using both DOUTA and DOUTB. Alternatively, a single
output pin of the user’s choice can be used. The SCLK input
first registered after the falling edges of the
CS
low indicating the end of a conversion. Once
.
The
pin can be brought low before the BUSY signal goes
CS
CS
signal provides the clock source for the serial interface. The
goes low to access data from the AD7366/AD7367. The falling
CS
is at a logic low
state the data bus is brought out of three-state. This feature can
be utilized to ensure that the MSB is valid on the falling edge of
edge of
takes the bus out of three-state and clocks out the
MSB of the conversion result. The data stream consists of
12 bits of data for the AD7366 and 14 bits of data for the
AD7367, MSB first. The first bit of the conversion result is
CS
BUSY by bring
low a minimum of t4 nanoseconds before the
CS
BUSY signal goes low. The dotted
Figure 23 illustrates this.
line in Figure 22 and
CS
valid on the first SCLK falling edge after the
falling edge.
CS
Alternatively, the
pin can be tied to a low logic state continu-
The subsequent 11-/13-bits of data for the AD7366/AD7367
respectively are clocked out on the falling edge of the SCLK
signal. A minimum of 12 clock pulses must be provided to
AD7366 to access each conversion result, while a minimum
of 14 clock pulses must be provided to AD7367 to access the
conversion result. Figure 2± shows how a 12 SCLK read is used
to access the conversion results while Figure 26 illustrates the
case for the AD7367 with a 14 SCLK read.
ously. Now the DOUT pins never enter three-state and the data
bus is continuously active. Under these conditions, the MSB of
the conversion result for the AD7366/AD7367 is available on
the falling edge of the BUSY signal. The next most significant
bit is available on the first SCLK falling edge after the BUSY
signal has gone low. This mode of operation enables the user to
read the MSB as soon as it is made available by the converter.
CS
t8
3
4
5
12
SCLK
1
2
t9
t7
t5
t6
t4
D
D
A
B
OUT
DB10
DB9
DB8
DB2
DB1
DB0
THREE-STATE
OUT
THREE-
STATE
DB11
Figure 25. Serial Interface Timing Diagram for the AD7366
CS
t8
3
4
5
14
SCLK
1
2
t9
t7
t5
t6
t4
D
A
OUT
DB12
DB11
DB10
DB2
DB1
DB0
D
B
THREE-STATE
OUT
THREE-
STATE
DB13
Figure 26. Serial Interface Timing Diagram for the AD7367
Rev. 0 | Page 22 of 28
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