AD7366/AD7367
SHUTDOWN MODE
POWER-UP TIMES
Shutdown mode is intended for use in applications where slow
throughput rates are required. Shutdown mode is suited to
applications where a series of conversions performed at a
relatively high throughput rate are followed by a long period
of inactivity and thus, shutdown. When the AD7366/AD7367
is in full power-down, all analog circuitry is powered down.
The AD7366/AD7367 have one power down mode, which has
already been described in detail in the Shutdown Mode section.
This section deals with the power-up time required when coming
out of this mode. It should be noted that the power-up times (as
explained in this section) apply with the recommended capaci-
tors in place on the DCAPA and DCAPB pins. To power up from
CNꢁST
CNꢁST
The falling edge of
initiates the conversion. The BUSY
shutdown,
must be brought high and remain high for a
output subsequently goes high to indicate that the conversion is
in progress. Once the conversion is completed, the BUSY output
minimum of 7ꢀ μs, as shown in Figure 24.
When power supplies are first applied to the AD7366/AD7367,
CNꢁST
returns low. If the
signal is at logic low when BUSY goes
CNꢁST
the ADC can power up with
logic state. Before attempting a valid conversion,
be brought high and remain high for the recommended power-
CNꢁST
in either the low or high
low then the part enters shutdown at the end of the conversion
phase. While the part is in shutdown mode the digital output
code from the last conversion on each ADC can still be read
CNꢁST
must
up time of 7ꢀ μs. Then
can be brought low to initiate a
CS
from the DOUT pins. To read the DOUT data,
low as described in the Serial Interface section. The DOUT pins
CS
must be brought
conversion. With the AD7366/AD7367 no dummy conversion
is required before valid data can be read from the DOUT pins.
If it is intended to place the part in shutdown mode when the
supplies are first applied, then the AD7366/AD7367 must be
powered up and a conversion initiated. However,
remain in the logic low state and when the BUSY signal goes
return to three-state once
To exit full power-down and to power up the AD7366/AD7367,
CNꢁST
is brought back to logic high.
CNꢁST
should
a rising edge of
time has elapsed,
is required. After the required power-up
CNꢁST
may be brought low again to initiate
low, the part enters shutdown.
another conversion, as shown in Figure 24 (see the Power-Up
Times section for power-up times associated with the AD7366/
AD7367).
Once supplies are applied to the AD7366/AD7367, sufficient
time must be allowed for any external reference to power up and
to charge the various reference buffer decoupling capacitors to
their final values.
tPOWER-UP
ENTERS SHUTDOWN
CNVST
BUSY
t2
tCONVERT
t3
CS
SCLK
SERIAL READ OPERATION
12
1
Figure 24. Autoshutdown Mode for AD7366
Rev. 0 | Page 21 of 28
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