AD7366/AD7367
VDRIVE
DRIVER AMPLIFIER CHOICE
The AD7366/AD7367 also have a ꢁDRIꢁE feature to control the
voltage at which the serial interface operates. ꢁDRIꢁE allows the
ADC to easily interface to both 3 ꢁ and ± ꢁ processors. For
example, if the AD7366/AD7367 was operated with a ꢁCC of
± ꢁ, the ꢁDRIꢁE pin could be powered from a 3 ꢁ supply, allow-
ing a large dynamic range with low voltage digital processors.
Thus, the AD7366/AD7367 could be used with the ±1ꢀ ꢁ input
range while still being able to interface to 3 ꢁ digital parts.
The AD7366/AD7367 have a total of four analog inputs, which
operate in single-ended mode. Both ADC’s analog inputs can
be programmed to one of the three analog input ranges. In
applications where the signal source is high impedance, it is
recommended to buffer the signal before applying it to the
ADC analog inputs. Figure 21 shows the configuration of the
AD7366/AD7367 in single-ended mode.
In applications where the THD and SNR are critical specifi-
cations, the analog input of the AD7366/AD7367 should be
driven from a low impedance source. Large source impedances
significantly affect the ac performance of the ADC and can
necessitate the use of an input buffer amplifier.
To achieve the maximum throughput rate of 1.12 MSPS for the
AD7366 or 1 MSPS for the AD7367, ꢁDRIꢁE must be greater than
or equal to 4.7± ꢁ, see Table 2 and Table 3. The maximum
throughput rate with the ꢁDRIꢁE voltage set to less than 4.7± ꢁ
and greater than 2.7 ꢁ is 1 MSPS for the AD7366 and 9ꢀꢀ kSPS
for the AD7367.
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance depends on the amount of THD that can be tolerated
in the application. The THD increases as the source impedance
increases and performance degrades. Figure 7 shows THD vs.
the analog input frequency for various source impedances.
Depending on the input range and analog input configuration
selected, the AD7366/AD7367 can handle source impedances as
illustrated in Figure 7.
REFERENCE
The AD7366/AD7367 can operate with either the internal 2.± ꢁ
on-chip reference or an externally applied reference. The logic
state of the REFSEL pin determines whether the internal refer-
ence is used. The internal reference is selected for both ADC
when the REFSEL pin is tied to logic high. If the REFSEL pin is
tied to GND then an external reference can be supplied through
the DCAPA and DCAPB pins. On power-up, the REFSEL pin must
be tied to either a low or high logic state for the part to operate.
Suitable reference sources for the AD7366/AD7367 include
AD78ꢀ, AD1±82, ADR431, REF193, and ADR391.
Due to the programmable nature of the analog inputs on the
AD7366/AD7367, the choice of op amp used to drive the
inputs is a function of the particular application and depends
on the analog input voltage ranges selected.
The internal reference circuitry consists of a 2.± ꢁ band gap
reference and a reference buffer. When operating the AD7366/
AD7367 in internal reference mode, the 2.± ꢁ internal reference
is available at the DCAPA and DCAPB pins, which should be
decoupled to AGND using a 68ꢀ nF capacitor. It is recom-
mended that the internal reference be buffered before applying
it elsewhere in the system. The internal reference is capable of
sourcing up to 1±ꢀ μA with an analog input range of ±1ꢀ ꢁ
and 7ꢀ μA for both the ±± ꢁ and ꢀ ꢁ to 1ꢀ ꢁ ranges.
The driver amplifier must be able to settle for a full-scale step
to a 14-bit level, ꢀ.ꢀꢀ61%, in less than the specified acquisition
time of the AD7366/AD7367. An op amp such as the AD8ꢀ21
meets this requirement when operating in single-ended mode.
The AD8ꢀ21 needs an external compensating NPO type of
capacitor. The AD8ꢀ22 can also be used in high frequency
applications where a dual version is required. For lower fre-
quency applications, recommended op amps are the AD797,
AD84±, and AD861ꢀ.
V+
If the internal reference operation is required for the ADC con-
version, the REFSEL pin must be tied to logic high on power-
up. The reference buffer requires 7ꢀ ꢃs to power up and charge
the 68ꢀ nF decoupling capacitor during the power-up time.
10µF
+5V
+10V/+5V
0.1µF
+
AGND
AD8021
V
A1
The AD7366/AD7367 is specified for a 2.± ꢁ to 3 ꢁ reference
range. When a 3 ꢁ reference is selected, the ranges are ±12 ꢁ,
±6 ꢁ, and ꢀ ꢁ to +12 ꢁ. For these ranges, the ꢁDD and ꢁSS
supply must be equal to or greater than the +12 ꢁ and −12 ꢁ
respectively.
V
V
CC
DD
–10V/–5V
1kꢀ
AD7366/
AD7367*
15pF
V
1kꢀ
SS
0.1µF
10µF
C
= 10pF
COMP
V–
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 21. Typical Connection Diagram with the AD8021 for Driving the
Analog Input
Rev. 0 | Page 19 of 28
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