AD7366/AD7367
MODES OF OPERATION
The mode of operation of the AD7366/AD7367 is selected by
CNꢁST
three-state, subsequently 12 SCLK cycles are required to read
the conversion result from the AD7366 while 14 SCLK cycles
are required to read from the AD7367. The DOUT lines return
the (logic) state of the
signal at the end of a conversion.
There are two possible modes of operation: normal mode and
shutdown mode. These modes of operation are designed to
provide flexible power management options, which can be
chosen to optimize the power dissipation/throughput rate
ratio for differing application requirements.
CS
CS
to three-state when
is brought high only. If
is left low
for a further 12 SCLK cycles for the AD7366 or 14 SCLK cycles
for the AD7367, the result from the other on chip ADC is also
accessed on the same DOUT line, as shown in Figure 27 and
Figure 28 (see the Serial Interface section).
NORMAL MODE
Once 24 SCLK cycles have elapsed for the AD7366 and 28
SCLK cycles for the AD7367, the DOUT line returns to three-
Normal mode is intended for applications needing fast
throughput rates because the user does not have to worry
about any power-up times (with the AD7366/AD7367
remaining fully powered at all times). Figure 22 shows the
general mode of operation of the AD7366 in normal mode,
while Figure 23 illustrates normal mode for the AD7367.
th
th
CS
state when
falling edge. If
returns to three-state at that point. Thus,
is brought high and not on the 24 or 28 SCLK
CS
is brought high prior to this, the DOUT line
CS
must be brought
high once the read is completed, as the bus does not auto-
matically return to three-state upon completion of the dual
result read.
CNꢁST
The conversion is initiated on the falling edge of
described in the Circuit Information section. To ensure that
CNꢁST
as
Once a data transfer is complete and DOUTA and DOUTB have
returned to three-state, another conversion can be initiated after
the part remains fully powered up at all times,
must be
CNꢁST
at logic state high prior to the BUSY signal going low. If
CNꢁST
the quiet time, tQUIET, has elapsed by bringing
low again.
is at logic state low when the BUSY signal goes low, the analog
circuitry powers down and the part ceases converting. The
BUSY signal remains high for the duration of the conversion.
CS
The
pin must be brought low to bring the data bus out of
t1
CNVST
tQUIET
t2
BUSY
tCONVERT
t3
CS
SCLK
SERIAL READ OPERATION
1
12
Figure 22. Normal Mode Operation for the AD7366
t1
CNVST
BUSY
tQUIET
t2
tCONVERT
t3
CS
SCLK
SERIAL READ OPERATION
1
14
Figure 23. Normal Mode Operation for the AD7367
Rev. 0 | Page 20 of 28
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