AD7366/AD7367
Unlike other bipolar ADCs, the AD7366/AD7367 do not have
a resistive analog input structure. On the AD73667/AD7366,
the bipolar analog signal is sampled directly onto the sampling
capacitor. This gives the AD7366/AD7367 high analog input
impedance. The analog input impedance can be calculated from
the following formula:
TYPICAL CONNECTION DIAGRAM
Figure 2ꢀ shows a typical connection diagram for the AD7366/
AD7367. In this configuration, the AGND pin is connected
to the analog ground plane of the system, and the DGND pin
is connected to the digital ground plane of the system. The
analog inputs on the AD7366/AD7367 accept bipolar single-
ended signals. The AD7366/AD7367 can operate with either
an internal or an external reference. In Figure 2ꢀ, the AD7366/
AD7367 is configured to operate with the internal 2.± ꢁ reference.
A 68ꢀ nF decoupling capacitor is required when operating with
the internal reference.
Z = 1/(fS × CS)
where:
fS is the sampling frequency.
CS is the sampling capacitor value.
CS depends on the analog input range chosen (see the Analog
Inputs section). When operating at 1 MSPS, the analog input
impedance is typically 26ꢀ kꢂ for the ±1ꢀ ꢁ range. As the
sampling frequency is reduced, the analog input impedance
further increases. As the analog input impedance increases, the
current required to drive the analog input therefore decreases
(see Figure 7 for more information).
The AꢁDD and DꢁDD pins are connected to a ± ꢁ supply voltage.
The ꢁDD and ꢁSS are the dual supplies for the high voltage analog
input structures. The voltage on these pins must be equal to
or greater than ±11.± ꢁ (see Table 8 for more information). The
ꢁDRIꢁE pin is connected to the supply voltage of the micro-
processor. The voltage applied to the ꢁDRIꢁE input controls the
voltage of the serial interface. ꢁDRIꢁE can be set to 3 ꢁ or ± ꢁ.
+
0.1µF
+5V SUPPLY
+11.5V TO +16.5V
SUPPLY
+
+
+
+
10µF
0.1µF
0.1µF
10µF
V
DV
AV
CC CC
+3V OR +5V SUPPLY
+
DD
V
DRIVE
+
V
V
A1
0.1µF
10µF
AD7366/
AD7367
A2
CS
ANALOG INPUTS ±10V,
±5V, AND 0V TO +10V
SCLK
CNVST
D
D
A
B
OUT
V
V
B1
OUT
BUSY
ADDR
B2
V
REFSEL
DGND
DRIVE
D
D
A
B
V
CAP
SERIAL
INTERFACE
+
680nF
CAP
+
680nF
AGND
SS
–16.5V TO –11.5V
SUPPLY
0.1µF
10µF
+
+
Figure 20. Typical Connection Diagram Using Internal Reference
Rev. 0 | Page 18 of 28
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