AD7366/AD7367
TMS320VC5506*
AD7366/
AD7367*
Table 13. The SPORT0 Receive Configuration 1 Register
(SPORT0_RCR1)
SCLK
CLKX0
CLKR0
CLKX1
CLKR1
DR0
Setting
Description
RCKFE = 1
LRFS = 1
RFSR = 1
Sample data with falling edge of RSCLK
Active low frame signal
Frame every word
Internal RFS used
D
D
A
B
OUT
DR1
OUT
IRFS = 1
CS
FSX0
FSR0
FSR1
INTn
RLSBIT = 0
RDTYPE = 00
IRCLK = 1
RSPEN = 1
SLEN = 1111
Receive MSB first
Zero fill
Internal receive clock
Receive enabled
16-bit data-word (or can be set to 1101 for
14-bit data-word)
BUSY
CNVST
XF
V
DRIVE
TFSR = RFSR = 1
V
*ADDITIONAL PINS OMITTED FOR CLARITY.
DD
Figure 31. Interfacing the AD7366/AD7367 to the TMS320VC5506
Table 14. The SPORT0 Receive Configuration 2 Register
(SPORT0_RCR2)
As with the previous interfaces, conversion can be initiated
from the TMS32ꢀꢁC±±ꢀ6 or from an external source, and the
processor is interrupted when the conversion sequence is
completed.
Setting
Description
RXSE = 1
Secondary side enabled
SLEN = 1111
16-bit data-word (or can be set to 1101 for
14-bit data-word)
AD7366/AD7367 TO DSP563xx
AD7366/AD7367 TO TMS320VC5506
The connection diagram in Figure 32 shows how the AD7366/
AD7367 can be connected to the enhanced synchronous serial
interface (ESSI) of the DSP±63xx family of DSPs from Motorola.
There are two on-board ESSIs, and each is operated in synchro-
nous mode (Bit SYN = 1 in the CRB register) with internally
generated word length frame sync for both TX and RX (Bit
FSL1 = ꢀ and Bit FSLꢀ = ꢀ in the CRB register).
The serial interface on the TMS32ꢀꢁC±±ꢀ6 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
CS
AD7366/AD7367. The
input allows easy interfacing between
the TMS32ꢀꢁC±±ꢀ6 and the AD7366/AD7367 without any glue
logic required. The serial ports of the TMS32ꢀꢁC±±ꢀ6 are set
up to operate in burst mode with internal CLKXꢀ (TX serial
clock on Serial Port ꢀ) and FSXꢀ (TX frame sync from Serial
Port ꢀ). The serial port control registers (SPC) must be setup
as shown in Table 1±.
Normal operation of the ESSI is selected by making MOD = ꢀ
in the CRB register. Set the word length to 16 by setting Bit
WL1 = 1 and Bit WLꢀ = ꢀ in the CRA register. The FSP bit in
the CRB register should be set to 1 so that the frame sync is
negative.
Table 15. Serial Port Control Register Set Up
SPC
FO
FSM
MCM
TXM
SPC0
SPC1
0
0
1
1
1
0
1
0
The connection diagram is shown in Figure 31. The ꢁDRIꢁE pin
of the AD7366/AD7367 takes the same supply voltage as that
of the TMS32ꢀꢁC±±ꢀ6. This allows the ADC to operate at a
higher voltage than its serial interface and, therefore, the
TMS32ꢀꢁC±±ꢀ6, if necessary.
Rev. 0 | Page 25 of 28
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