AD7366/AD7367
In the example shown in Figure 32, the serial clock is taken
from the ESSIꢀ so the SCKꢀ pin must be set as an output
(SCKD = 1) while the SCK1 pin is set as an input (SCKD = ꢀ).
The frame sync signal is taken from SCꢀ2 on ESSIꢀ, so SCD2 = 1,
while on ESSI1, SCD2 = ꢀ; therefore, SC12 is configured as an
input. The ꢁDRIꢁE pin of the AD7366/AD7367 takes the same
supply voltage as that of the DSP±63xx. This allows the ADC
to operate at a higher voltage than its serial interface and,
therefore, the DSP±63xx, if necessary.
DSP563xx*
SCK0
AD7366/
AD7367*
SCLK
SCK1
SRD0
SRD1
SC02
SC12
D
D
A
OUT
B
OUT
CS
BUSY
IRQ
N
CNVST
PB
N
V
DRIVE
V
*ADDITIONAL PINS OMITTED FOR CLARITY.
DD
Figure 32. Interfacing the AD7366/AD7367 to the DSP563xx
Rev. 0 | Page 26 of 28
ADI [ ADI ]
