AD7366/AD7367
MICROPROCESSOR INTERFACING
The serial interface on the AD7366/AD7367 allows the parts
to be directly connected to a range of different microprocessors.
This section explains how to interface the AD7366/AD7367
with some more common microcontrollers and DSP serial
interface protocols.
ADSP-218x*
SCLK0
AD7366/
AD7367*
SCLK
SCLK1
TFS0
RFS0
RFS1
DR0
CS
AD7366/AD7367 TO ADSP-218x
D
D
A
The ADSP-218x family of DSPs interfaces directly to the
AD7366/AD7367 without any glue logic required. The ꢁDRIꢁE
pin of the AD7366/AD7367 takes the same supply voltage as
that of the ADSP-218x. This allows the ADC to operate at a
higher supply voltage than its serial interface and therefore, the
ADSP-218x, if necessary. This example shows both DOUTA and
OUT
B
DR1
IRQ
OUT
BUSY
CNVST
FLO
V
DRIVE
D
OUTB of the AD7366/AD7367 connected to both serial ports
V
DD
*ADDITIONAL PINS OMITTED FOR CLARITY.
of the ADSP-218x. The SPORTꢀ and SPORT1 control registers
should be set up as shown in Table 11 and Table 12.
Figure 29. Interfacing the AD7366/AD7367 to the ADSP-218x
The AD7366/AD7367 BUSY line provides an interrupt to
the ADSP-218x when the conversion is complete. The conver-
sion results can then be read from the AD7366/AD7367 using
Table 11. SPORT0 Control Register Setup
Setting
Description
TFSW = RFSW = 1
INVRFS = INVTFS = 1
DTYPE = 00
Alternate framing
Active low frame signal
Right justify data
IRQ
a read operation. When an interrupt is received on
from
the BUSY signal, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and, hence,
the reading of data.
SLEN = 1111
16-bit data-word (or can be set to 1101
for 14-bit data-word)
ISCLK = 1
TFSR = RFSR = 1
IRFS = 0
Internal serial clock
Frame every word
AD7366/AD7367 TO ADSP-BF53x
The ADSP-BF±3x family of DSPs interfaces directly to the
AD7366/AD7367 without any glue logic required. The avail-
ability of secondary receive registers on the serial ports of the
Blackfin® DSPs means only one serial port is necessary to read
from both DOUTA and DOUTB pins simultaneously. Figure 3ꢀ
shows both DOUTA and DOUTB of the AD7366/AD7367 con-
nected to Serial Port ꢀ of the ADSP-BF±3x. The SPORTꢀ
Receive Configuration 1 register and SPORTꢀ Receive
Configuration 2 register should be set up as outlined in
Table 13 and Table 14.
ITFS = 1
Table 12. SPORT1 Control Register Setup
Setting
Description
TFSW = RFSW = 1
INVRFS = INVTFS = 1
DTYPE = 00
Alternate framing
Active low frame signal
Right justify data
16-bit data-word (or can be set to 1101
for 14-bit data-word)
SLEN = 1111
ISCLK = 0
TFSR = RFSR = 1
IRFS = 0
External serial clock
Frame every word
ADSP-BF53x*
SPORT0
AD7366/
AD7367*
SERIAL
DEVICE A
(PRIMARY)
D
A
DR0PRI
RCLK0
OUT
ITFS = 1
SCLK
CS
BUSY
RFS0
The connection diagram is shown in Figure 29. The ADSP-218x
has the TFSꢀ and RFSꢀ of the SPORTꢀ and the RFS1 of SPORT1
tied together. TFSꢀ is set as an output, and both RFSꢀ and RFS1
are set as inputs. The DSP operates in alternate framing mode,
and the SPORT control register is set up as described in
Table 13 and Table 14. The frame synchronization signal
RXINTS
CNVST
PF
N
D
B
DR0SEC
OUT
SERIAL
DEVICE B
(SECONDARY)
V
DRIVE
CS
generated on the TFS is tied to
.
V
DD
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 30. Interfacing the AD7366/AD7367 to the ADSP-BF53x
Rev. 0 | Page 24 of 28
ADI [ ADI ]
