AD7366/AD7367
V
Table 10. LSB Sizes for Each Analog Input Range
AD7366 AD7367
DD
D
C2
R1
Input
Full-Scale
LSB Size
(mV)
Full-Scale
LSB Size
(mV)
V
0
IN
Range
C1
Range
Range
D
10 V
5 V
0 V to 10 V
20 V/4096
10 V/4096
10 V/4096
4.88
2.44
2.44
20 V/16384
10 V/16384
10 V/16384
1.22
0.61
0.61
V
SS
Figure 18. Equivalent Analog Input Structure
The AD7366/AD7367 can handle true bipolar input voltages.
The analog input can be set to one of three ranges: ±1ꢀ ꢁ, ±± ꢁ,
or ꢀ ꢁ to 1ꢀ ꢁ. The logic levels on Pin RANGEꢀ and Pin RANGE1
determine which input range is selected as outlined in Table 8.
These range bits should not be changed during the acquisition
time prior to a conversion, but can change at any other time.
011...111
011...110
000...001
000...000
111...111
Table 8. Analog Input Range Selection
RANGE1
RANGE0
Range Selected
100...010
100...001
100...000
0
0
1
1
0
1
0
1
10 V
5 V
0 V to 10 V
Do not program
–FSR/2 + 1LSB
+FSR/2 – 1LSB
0V
ANALOG INPUT
Figure 19. Transfer Characteristic
The AD7366/AD7367 require ꢁDD and ꢁSS dual supplies for the
high voltage analog input structures. These supplies must be
equal to or greater than ±11.± ꢁ. See Table 7 for the require-
ments on these supplies. The AD7366/AD7367 require a low
voltage 4.7± ꢁ to ±.2± ꢁ AꢁCC supply to power the ADC core,
a 4.7± ꢁ to ±.2± ꢁ DꢁCC supply for digital power, and a 2.7 ꢁ
to ±.2± ꢁ ꢁDRIꢁE supply for interface power.
Track-and-Hold
The track-and-hold on the analog input of the AD7366/AD7367
allows the ADC to accurately convert an input sine wave of full-
scale amplitude to 12-/14-bit accuracy. The input bandwidth of
the track-and-hold is greater than the Nyquist rate of the ADC.
The AD7366/AD7367 can handle frequencies up to 3± MHz.
The track-and-hold enters its tracking mode once the BUSY
signal goes low after the
Channel selection is made via the ADDR pin as shown in
Table 9. The logic level on the ADDR pin is latched on the
rising edge of the BUSY signal for the next conversion, not
the one in progress. When power is first supplied to the
AD7366/AD7367 the default channel selection is ꢁA1 and ꢁB1.
CS
falling edge. The time required to
acquire an input signal depends on how quickly the sampling
capacitor is charged. With zero source impedance, 14ꢀ ns is suffi-
cient to acquire the signal to the 12-bit for the AD7366 and the
14-bit level for the AD7367. The acquisition time for the ±1ꢀ ꢁ,
±± ꢁ, and ꢀ ꢁ to +1ꢀ ꢁ ranges to settle to within ±½ LSB is
typically 14ꢀ ns. The ADC goes back into hold mode on the
Table 9. Channel Selection
ADDR
Channels Selected
CNꢁST
falling edge of
.
0
1
VA1, VB1
VA2, VB2
The acquisition time required is calculated using the following
formula:
TRANSFER FUNCTION
t
ACQ = 1ꢀ × ((RSOURCE + R) C)
The output coding of the AD7366/AD7367 is twos complement.
The designed code transitions occur at successive integer LSB
values (that is, 1 LSB, 2 LSB, and so on). The LSB size is dependent
on the analog input range selected. The ideal transfer charac-
teristic is shown in Figure 19.
where:
C is the sampling capacitance.
R is the resistance seen by the track-and-hold amplifier looking
at the input.
RSOURCE should include any extra source impedance on the
analog input.
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