AD7366/AD7367
THEORY OF OPERATION
CIRCUIT INFORMATION
CONVERTER OPERATION
The AD7366/AD7367 have two successive approximation
ADCs, each based around two capacitive DACs. Figure 16 and
Figure 17 show simplified schematics of an ADC in acquisition
and conversion phases. The ADC is comprised of control logic,
a SAR, and a capacitive DAC. In Figure 16 (the acquisition phase),
SW2 is closed and SW1 is in Position A, the comparator is held
in a balanced condition, and the sampling capacitor arrays
acquire the signal on the input.
The AD7366/AD7367 are fast, dual, 2-channel, 12-/14-bit,
bipolar input, simultaneous sampling, serial ADCs. The
AD7366/AD7367 can accept bipolar input ranges of ±1ꢀ ꢁ
and ±± ꢁ. It can also accept a ꢀ ꢁ to 1ꢀ ꢁ unipolar input range.
The AD7366/AD7367 requires ꢁDD and ꢁSS dual supplies for
the high voltage analog input structure. These supplies must
be equal to or greater than 11.± ꢁ. See Table 7 for the minimum
requirements on these supplies for each analog input range. The
AD7366/AD7367 require a low voltage of 4.7± ꢁ to ±.2± ꢁ ꢁCC
supply to power the ADC core.
CAPACITIVE
DAC
A
Table 7. Reference and Supply Requirements for Each
Analog Input Range
V
IN
CONTROL
LOGIC
SW1
B
SW2
Selected
Analog Input Reference
Range (V)
Full-Scale
Input
Range (V)
COMPARATOR
Minimum
VDD/VSS (V)
Voltage (V)
AVCC (V)
AGND
10
2.5
3.0
2.5
3.0
2.5
3.0
10
12
5
5
5
5
5
5
11.5
12
Figure 16. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 17), SW2
opens and SW1 moves to Position B, causing the comparator
to become unbalanced. The control logic and the charge redis-
tribution DAC is used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is
balanced again, the conversion is complete. The control logic
generates the ADC output code.
5
5
11.5
11.5
11.5
12
6
0 to 10
0 to 10
0 to 12
The AD7366/AD7367 contain two on-chip, track-and-hold
amplifiers, two successive approximation ADCs, and a serial
interface with two separate data output pins. It is housed in a
24-lead TSSOP, offering the user considerable space-saving
advantages over alternative solutions. The AD7366/AD7367
require a
edge of
and the conversions are initiated. The BUSY signal goes high to
indicate that the conversions are taking place. The clock source
for each successive approximation ADC is provided by an internal
oscillator. The BUSY signal goes low to indicate the end of
conversion. On the falling edge of BUSY, the track-and-hold
returns to track mode. Once the conversion is finished, the
serial clock input accesses data from the part.
CAPACITIVE
DAC
CNꢁST
signal to start conversion. On the falling
CNꢁST
both track-and-holds are placed into hold mode
A
V
IN
CONTROL
LOGIC
SW1
B
SW2
COMPARATOR
AGND
Figure 17. ADC Conversion Phase
ANALOG INPUTS
Each ADC in the AD7366/AD7367 has two single-ended
analog inputs. Figure 18 shows the equivalent circuit of the
analog input structure of the AD7366/AD7367. The two diodes
provide ESD protection. Care must be taken to ensure that the
analog input signals never exceed the supply rails by more than
3ꢀꢀ mꢁ. This causes these diodes to become forward-biased
and starts conducting current into the substrate. These diodes
can conduct up to 1ꢀ mA without causing irreversible damage
to the part. The resistors are lumped components made up of
the on resistance of the switches. The value of these resistors is
typically about 17ꢀ Ω. Capacitor C1 can primarily be attributed
to pin capacitance while Capacitor C2 is the sampling capacitor
of the ADC. The total lumped capacitance of C1 and C2 is
approximately 9 pF for the ±1ꢀ ꢁ input range and approxi-
mately 13 pF for all other input ranges.
The AD7366/AD7367 have an on-chip 2.± ꢁ reference that
can be disabled when an external reference is preferred. If
the internal reference is to be used elsewhere in a system, then
the output from DCAPA and DCAPB must first be buffered. On
power-up, the REFSEL pin must be tied to either a high or low
logic state to select either the internal or external reference option.
If the internal reference is the preferred option, the user must
tie the REFSEL pin logic high. Alternatively, if REFSEL is tied to
GND then an external reference can be supplied to both ADCs
through DCAPA and DCAPB pins.
The analog inputs are configured as two single-ended inputs for
each ADC. The various different input voltage ranges can be
selected by programming the RANGE bits as shown in Table 8.
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