ADV7390/ADV7391/ADV7392/ADV7393
Table 96. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out
Table 100. 8-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
0x02
0x30
0x31
0x10
0x04
0x01
RGB output enabled. RGB output sync
enabled.
0x30
0x31
0x1C
0x01
625p @ 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
525p @ 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
Pixel data valid.
Pixel data valid.
Table 97. 16-Bit 625p YCrCb In, RGB Out
Subaddress Setting Description
Table 101. 10-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
0x02
0x30
0x10
0x04
RGB output enabled. RGB output sync
enabled.
0x30
0x31
0x18
0x01
625p @ 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
525p @ 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
Pixel data valid.
0x31
0x33
0x01
0x6C
Pixel data valid.
10-bit input enabled.
Table 98. 8-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
Table 102. 8-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
All DACs enabled. PLL enabled (8×).
0x30
0x31
0x04
0x01
525p @ 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
Pixel data valid.
0x30
0x31
0x1C
0x01
625p @ 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
Pixel data valid.
Table 99. 10-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
Table 103. 10-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
All DACs enabled. PLL enabled (8×).
0x30
0x04
525p @ 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x31
0x33
0x01
0x6C
Pixel data valid.
0x30
0x1C
625p @ 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
10-bit input enabled.
0x31
0x33
0x01
0x6C
Pixel data valid.
10-bit input enabled.
Rev. 0 | Page 91 of 96
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