ADV7390/ADV7391/ADV7392/ADV7393
Table 117. 8-Bit 720p YCrCb In (EAV/SAV), RGB Out
Table 120. 10-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
All DACs enabled. PLL enabled (4×).
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x30
0x31
0x10
0x2C
0x01
RGB output enabled. RGB output sync
enabled.
0x30
0x6C
1080i @ 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
720p @ 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x33
0x01
0x6C
Pixel data valid. 4× oversampling.
10-bit input enabled.
Pixel data valid. 4× oversampling.
Table 121. 8-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
Table 118. 10-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
All DACs enabled. PLL enabled (4×).
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x30
0x31
0x10
0x6C
0x01
RGB output enabled. RGB output sync
enabled.
0x02
0x30
0x10
0x2C
RGB output enabled. RGB output sync
enabled.
1080i @ 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
720p @ 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
0x31
0x33
0x01
0x6C
Pixel data valid. 4× oversampling.
10-bit input enabled.
Table 122. 10-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
Table 119. 8-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
All DACs enabled. PLL enabled (4×).
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x30
0x10
0x6C
RGB output enabled. RGB output sync
enabled.
0x30
0x31
0x6C
0x01
1080i @ 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
1080i @ 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
0x31
0x33
0x01
0x6C
Pixel data valid. 4× oversampling.
10-bit input enabled.
Rev. 0 | Page 94 of 96
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