ADV7390/ADV7391/ADV7392/ADV7393
Table 112. 16-Bit 1080i YCrCb In, YPrPb Out
Subaddress Setting Description
Table 107. 16-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x18
Software reset.
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x2C
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
1080i @ 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
720p @ 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
0x31
0x01
Pixel data valid. 4× oversampling.
Table 113. 16-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
Table 108. 16-Bit 720p YCrCb In, YPrPb Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x28
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
720p @ 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x30
0x31
0x6C
0x01
1080i @ 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
Pixel data valid. 4× oversampling.
Table 109. 16-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
Table 114. 16-Bit 1080i YCrCb In, RGB Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
RGB output enabled. RGB output sync
enabled.
0x30
0x31
0x2C
0x01
720p @ 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x30
0x31
0x18
0x01
1080i @ 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Pixel data valid. 4× oversampling.
Table 110. 16-Bit 720p YCrCb In, RGB Out
Subaddress Setting Description
Table 115. 8-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
0x30
0x31
0x2C
0x01
720p @ 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x30
0x31
0x28
0x01
720p @ 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Pixel data valid. 4× oversampling.
Table 116. 10-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
Table 111. 16-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x6C
Software reset.
All DACs enabled. PLL enabled (4×).
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
1080i @ 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x30
0x2C
720p @ 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
0x31
0x33
0x01
0x6C
Pixel data valid. 4× oversampling.
10-bit input enabled.
Rev. 0 | Page 93 of 96
ADI [ ADI ]
