ADV7390/ADV7391/ADV7392/ADV7393
Table 105. 10-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
Table 104. 8-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x17
0x00
0x01
0x02
0x1C
0x20
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x30
0x10
0x1C
RGB output enabled. RGB output sync
enabled.
625p @ 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
0x02
0x30
0x31
0x10
0x1C
0x01
RGB output enabled. RGB output sync
enabled.
625p @ 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
0x31
0x33
0x01
0x6C
Pixel data valid.
10-bit input enabled.
Pixel data valid.
HIGH DEFINITION
Table 106. HD Configuration Scripts
Input Format
Input Data Width
Synchronization Format
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
HSYNC VSYNC
/
EAV/SAV
HSYNC VSYNC
/
Input Color Space
YCrCb
YCrCb
YCrCb
YCrCb
Output Color Space
Table Number
Table 115
Table 117
Table 116
Table 118
Table 107
Table 108
Table 109
Table 110
720p
720p
720p
720p
720p
720p
8-Bit DDR
8-Bit DDR
YPrPb
RGB
YPrPb
RGB
YPrPb
YPrPb
RGB
10-Bit DDR
10-Bit DDR
16-Bit SDR
16-Bit SDR
16-Bit SDR
16-Bit SDR
YCrCb
YCrCb
720p
720p
YCrCb
YCrCb
RGB
1080i
1080i
1080i
1080i
1080i
1080i
1080i
1080i
8-Bit DDR
8-Bit DDR
10-Bit DDR
10-Bit DDR
16-Bit SDR
16-Bit SDR
16-Bit SDR
16-Bit SDR
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YPrPb
RGB
YPrPb
RGB
YPrPb
YPrPb
RGB
Table 119
Table 121
Table 120
Table 122
Table 111
Table 112
Table 113
Table 114
HSYNC VSYNC
/
EAV/SAV
HSYNC VSYNC
RGB
/
Rev. 0 | Page 92 of 96
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