ADV7390/ADV7391/ADV7392/ADV7393
ENHANCED DEFINITION
Table 89. ED Configuration Scripts
Input Format
Input Data Width
Synchronization Format
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
HSYNC VSYNC
/
EAV/SAV
HSYNC VSYNC
/
Input Color Space
YCrCb
YCrCb
YCrCb
YCrCb
Output Color Space
Table Number
Table 98
Table 100
Table 99
Table 101
Table 90
Table 91
525p
525p
525p
525p
525p
525p
8-Bit DDR
8-Bit DDR
YPrPb
RGB
YPrPb
RGB
YPrPb
YPrPb
RGB
10-Bit DDR
10-Bit DDR
16-Bit SDR
16-Bit SDR
16-Bit SDR
16-Bit SDR
YCrCb
YCrCb
525p
525p
YCrCb
YCrCb
Table 92
Table 93
RGB
625p
625p
625p
625p
625p
625p
625p
625p
8-Bit DDR
8-Bit DDR
10-Bit DDR
10-Bit DDR
16-Bit SDR
16-Bit SDR
16-Bit SDR
16-Bit SDR
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YPrPb
RGB
YPrPb
RGB
YPrPb
YPrPb
RGB
Table 102
Table 104
Table 103
Table 105
Table 94
Table 95
Table 96
Table 97
HSYNC VSYNC
/
EAV/SAV
HSYNC VSYNC
RGB
/
Table 90. 16-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
Table 93. 16-Bit 525p YCrCb In, RGB Out
Subaddress Setting Description
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x04
Software reset.
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
525p @ 59.94 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
RGB output enabled. RGB output sync
enabled.
0x31
0x01
Pixel data valid.
0x30
0x31
0x00
0x01
525p @ 59.94 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
Table 91. 16-Bit 525p YCrCb In, YPrPb Out
Subaddress Setting Description
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x00
Software reset.
Table 94. 16-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x1C
Software reset.
525p @ 59.94 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
0x31
0x01
Pixel data valid.
625p @ 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 92. 16-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x02
0x1C
0x10
0x10
Software reset.
Table 95. 16-Bit 625p YCrCb In, YPrPb Out
Subaddress Setting Description
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
0x17
0x00
0x01
0x30
0x02
0x1C
0x10
0x18
Software reset.
RGB output enabled. RGB output sync
enabled.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
0x30
0x31
0x04
0x01
525p @ 59.94 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
625p @ 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
0x31
0x01
Pixel data valid.
Rev. 0 | Page 90 of 96
ADI [ ADI ]
