ADV7390/ADV7391/ADV7392/ADV7393
Table 67. 10-Bit 525i YCrCb In (EAV/SAV), RGB Out
Table 70. 16-Bit 525i YCrCb In, RGB Out
Subaddress Setting Description
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x02
0x1C
0x00
0x10
Software reset.
0x17
0x00
0x01
0x02
0x02
0x1C
0x00
0x10
Software reset
All DACs enabled. PLL enabled (16×).
SD input mode.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
RGB output enabled. RGB output sync
enabled.
0x80
0x82
0x10
0xC9
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x80
0x82
0x10
0xC9
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
0x88
0x10
10-bit input enabled.
0x88
0x8A
0x08
0x0C
16-bit input enabled.
Timing Mode 2 (Slave). HSYNC/VSYNC
synchronization.
Table 68. 10-Bit 525i YCrCb In, RGB Out
Subaddress Setting Description
Table 71. 16-Bit 525i RGB In, YPrPb Out
Subaddress Setting Description
0x17
0x00
0x01
0x02
0x02
0x1C
0x00
0x10
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
0x17
0x00
0x01
0x80
0x02
0x1C
0x00
0x10
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
0x80
0x82
0x10
0xC9
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
0x82
0xC9
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
0x88
0x8A
0x10
0x0C
10-bit input enabled.
0x87
0x88
0x8A
0x80
0x08
0x0C
RGB input enabled.
16-bit input enabled.
Timing Mode 2 (Slave). HSYNC/VSYNC
synchronization.
Timing Mode 2 (Slave). HSYNC/VSYNC
synchronization.
Table 69. 16-Bit 525i YCrCb In, YPrPb Out
Subaddress Setting Description
Table 72. 16-Bit 525i RGB In, CVBS/Y-C Out
0x17
0x00
0x01
0x80
0x02
0x1C
0x00
0x10
Software reset.
Subaddress Setting Description
All DACs enabled. PLL enabled (16×).
SD input mode.
0x17
0x00
0x01
0x80
0x02
0x1C
0x00
0x10
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
NTSC standard. SSAF luma filter
0x82
0xC9
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. pedestal enabled.
enabled. 1.3 MHz chroma filter enabled.
0x82
0xCB
Pixel data valid. CVBS/S-Video out. SSAF
PrPb filter enabled. Active video edge
control enabled. Pedestal enabled.
0x88
0x8A
0x08
0x0C
16-bit input enabled.
HSYNC VSYNC
Timing Mode 2 (Slave).
synchronization.
/
0x87
0x88
0x8A
0x80
0x08
0x0C
RGB input enabled.
16-bit input enabled.
Timing Mode 2 (Slave). HSYNC/VSYNC
synchronization.
Rev. 0 | Page 86 of 96
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