ADV7390/ADV7391/ADV7392/ADV7393
TIMING DIAGRAMS
The following abbreviations are used in Figure 2 to Figure 9.
In addition, refer to Table 30 for the ADV7390/ADV7391 input
configuration and Table 31 for the ADV7392/ADV7393 input
configuration.
•
•
•
•
•
•
t9 = Clock high time
t10 = Clock low time
t11 = Data setup time
t12 = Data hold time
t13 = Control output access time
t14 = Control output hold time
CLKIN
t12
t9
t10
CONTROL
INPUTS
HSYNC
VSYNC
IN SLAVE MODE
Y0
t11
Y1
Y2
PIXEL PORT
Cb0
Cr0
Cb2
t13
Cr2
CONTROL
OUTPUTS
IN MASTER/SLAVE MODE
t14
Figure 2. SD Input, 8-/10-Bit 4:2:2 YCrCb (Input Mode 000)
CLKIN
t9
t
t12
10
CONTROL
INPUTS
HSYNC
VSYNC
IN SLAVE MODE
Y2
Y0
Y1
Y3
PIXEL PORT
PIXEL PORT
Cb2
Cb0
Cr0
Cr2
t11
t13
CONTROL
OUTPUTS
IN MASTER/SLAVE MODE
t14
Figure 3. SD Input, 16-Bit 4:2:2 YCrCb (Input Mode 000)
Rev. 0 | Page 9 of 96
ADI [ ADI ]
