ADV7390/ADV7391/ADV7392/ADV7393
TIMING DIAGRAMS
The following abbreviations are used in Figure 2 to Figure 9.
•
•
•
•
•
•
t
9
= Clock high time
t
10
= Clock low time
t
11
= Data setup time
t
12
= Data hold time
t
13
= Control output access time
t
14
= Control output hold time
In addition, refer to Table 30 for the ADV7390/ADV7391 input
configuration and Table 31 for the ADV7392/ADV7393 input
configuration.
CLKIN
t
9
CONTROL
INPUTS
HSYNC
VSYNC
t
10
t
12
IN SLAVE MODE
PIXEL PORT
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
t
11
CONTROL
OUTPUTS
t
13
IN MASTER/SLAVE MODE
t
14
Figure 2. SD Input, 8-/10-Bit 4:2:2 YCrCb (Input Mode 000)
CLKIN
t
9
CONTROL
INPUTS
HSYNC
VSYNC
t
10
t
12
IN SLAVE MODE
PIXEL PORT
Y0
Y1
Y2
Y3
PIXEL PORT
Cb0
Cr0
Cb2
Cr2
t
11
CONTROL
OUTPUTS
t
13
IN MASTER/SLAVE MODE
06234-002
t
14
Figure 3. SD Input, 16-Bit 4:2:2 YCrCb (Input Mode 000)
Rev. 0 | Page 9 of 96
06234-003
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