ADV7390/ADV7391/ADV7392/ADV7393
DIGITAL TIMING SPECIFICATIONS
V
DD
= 1.71 V to 1.89 V, PV
DD
= 1.71 V to 1.89 V, V
AA
= 2.6 V to 3.465 V, V
DD_IO
= 2.97 V to 3.63 V.
All specifications T
MIN
to T
MAX
(−40°C to +85°C), unless otherwise noted.
Table 7.
Parameter
VIDEO DATA AND VIDEO CONTROL PORT
2, 3
Data Input Setup Time, t
11 4
Conditions
1
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz)
Min
2.1
2.3
2.3
1.7
1.0
1.1
1.1
1.0
2.1
2.3
1.7
1.0
1.1
1.0
12
10
4.0
3.5
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Input Hold Time, t
124
Control Input Setup Time, t
114
Control Input Hold Time, t
124
Control Output Access Time, t
134
Control Output Hold Time, t
144
PIPELINE DELAY
5
SD
1
CVBS/YC Outputs (2×)
CVBS/YC Outputs (8×)
CVBS/YC Outputs (16×)
Component Outputs (2×)
Component Outputs (8×)
Component Outputs (16×)
ED
1
Component Outputs (1×)
Component Outputs (4×)
Component Outputs (8×)
HD
1
Component Outputs (1×)
Component Outputs (2×)
Component Outputs (4×)
RESET CONTROL
RESET Low Time
1
2
SD oversampling disabled
SD oversampling disabled
SD oversampling enabled
SD oversampling disabled
SD oversampling disabled
SD oversampling enabled
ED oversampling disabled
ED oversampling disabled
ED oversampling enabled
HD oversampling disabled
HD oversampling disabled
HD oversampling enabled
100
68
79
67
78
69
84
41
49
46
40
42
44
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
ns
SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
Video Data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391.
3
Video Control: HSYNC and VSYNC.
4
Guaranteed by characterization.
5
Guaranteed by design.
Rev. 0 | Page 7 of 96
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