ADV7390/ADV7391/ADV7392/ADV7393
DIGITAL TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 7.
Parameter
VIDEO DATA AND VIDEO CONTROL PORT2, 3
Data Input Setup Time, t11
Conditions1
Min
Typ
Max
Unit
4
SD
2.1
2.3
2.3
1.7
1.0
1.1
1.1
1.0
2.1
2.3
1.7
1.0
1.1
1.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
4
Data Input Hold Time, t12
4
Control Input Setup Time, t11
4
Control Input Hold Time, t12
4
Control Output Access Time, t13
12
10
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz)
SD
4
Control Output Hold Time, t14
4.0
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) 3.5
PIPELINE DELAY5
SD1
CVBS/YC Outputs (2×)
CVBS/YC Outputs (8×)
CVBS/YC Outputs (16×)
Component Outputs (2×)
Component Outputs (8×)
Component Outputs (16×)
ED1
SD oversampling disabled
SD oversampling disabled
SD oversampling enabled
SD oversampling disabled
SD oversampling disabled
SD oversampling enabled
68
79
67
78
69
84
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
Component Outputs (1×)
Component Outputs (4×)
Component Outputs (8×)
HD1
ED oversampling disabled
ED oversampling disabled
ED oversampling enabled
41
49
46
clock cycles
clock cycles
clock cycles
Component Outputs (1×)
Component Outputs (2×)
Component Outputs (4×)
RESET CONTROL
HD oversampling disabled
HD oversampling disabled
HD oversampling enabled
40
42
44
clock cycles
clock cycles
clock cycles
RESET Low Time
100
ns
1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
2 Video Data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391.
3 Video Control:
and
.
HSYNC
VSYNC
4 Guaranteed by characterization.
5 Guaranteed by design.
Rev. 0 | Page 7 of 96
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